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Introduction


Plenty of Room at the bottom??

Currently at 45 nm process node and soon to be on 28 nm
Lithography was seen to be a major obstacle (dealt with using Immersion or X/EUV)
Moore’s Law still holding but for how long?
Transistors on die doubling and so is the Fab cost (Standing at close to 5bn for latest tech)

Materials Innovations

STI (Shallow Trench Isolation), CMP (Chemical Mechanical Polishing) and other process enhancements are now part of all manufacturing
Cu Interconnects replacing Al
Low-K dielectric for successive metalization
High-K Oxide for the Gate
Metal Gate replacing Polysilicon