04-07-2015, 10:47 AM
please send ppt about chip morphing technology quickly.
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chip morphing ppt
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please send ppt about chip morphing technology quickly.
04-07-2015, 02:32 PM
chip morphing ppt
Abstract
Engineering is a study of tradeoffs. In computer engineering the tradeoff has traditionally been between performance, measured in instructions per second, and price. Because of fabrication technology, price is closely related to chip size and transistor count. With the emergence of embedded systems, a new tradeoff has become the focus of design.Chip Morphing.Seminar Energy performance compromise: Engineering is a review of compromise. In computer engineering trade-off has always been between the performance measured in instructions per second, and the price. With the manufacturing technology, the price is closely related to the size of the chip and the number of transistors. With the emergence of embedded systems, a new equilibrium has been focused on the design. This new balance between performance and power or energy consumption. The requirements for computing the embedded systems have generally been more modest, and therefore the power output of compromises tend to be a balancing of power. "High Performance" and "energy efficiency" has been generally accepted concepts.Morph: Objectives and rationale of the project highlighted Morph, a part of the Power Aware Computing / Communication (parcels) initiative. In addition, several mechanisms to improve performance substantially, Morph project gave birth to the notion of 'changing gear', as an analogy, run time of reorganization. Morph project was to study a series of micro-architecture techniques for achieving this, as the morphable cache hierarchies and exploit the bit-slice of inactivity. One technique, multi-cluster architectures, has a direct predecessor of this work. In addition, micro-architectural changes that took place Morph realistic embedded applications, which may have the power to restrict. Also impact the design of power system is designed to run knowledge. This new tradeoff is between performance and power or energy consumption. The computational requirements of early embedded systems were generally more modest, and so the performance-power tradeoff tended to be weighted towards power. "High performance" and "energy efficient" were generally opposing concepts.
Introduction
Engineering is a study of tradeoffs. In computer engineering the tradeoff has traditionally been between performance, measured in instructions per second, and price. Because of fabrication technology, price is closely related to chip size and transistor count. With the emergence of embedded systems, a new tradeoff has become the focus of design. This new tradeoff is between performance and power or energy consumption. The computational requirements of early embedded systems were generally more modest, and so the performance-power tradeoff tended to be weighted towards power. “High performance” and “energy efficient” were generally opposing concepts. However, new classes of embedded applications are emerging which not only have significant energy constraints, but also require considerable computational resources. Devices such as space rovers, cell phones, automotive control systems, and portable consumer electronics all require or can benefit from high-performance processors. The future generations of such devices should continue this trend.
Challenges
Traditionally, performance has been improved by increasing the complexity of a micro-architecture. Unfortunately, power reduction has traditionally been accomplished by reducing processor complexity. Resolving these opposing demands is the primary challenge for low power high performance architectures.This growth in processor complexity is clearly demonstrated by the growth in the number of transistors in a processor. This complexity has taken many forms, such as multiple levels of cache, multiple functional units, and out of order execution. Though these techniques increase performance, they expend energy and experience diminishing returns. Indeed, it would appear that complex superscalar designs inherently contain too much overhead to be energy efficient.
IPC, EPI and EPC
Three key ratios are the focus to high-performance and low-power processor design: instructions per cycle (IPC), energy per instruction (EPI), and energy per cycle (EPC). These metrics can determine if a processor can provide high-performance, if it can do so in a power efficient manner, and if it dissipates little power even when high-performance is not required.IPC is the first level estimate of architectural speed. If a processor does not contain any features which would inherently limit the clock speed, IPC can provide a good estimate of actual performance. If power consumption were not an issue, then IPC would be the primary metric. EPI gives the most direct measure of energy efficiency. For embedded applications, energy measurement is generally more useful than power estimation because embedded applications are more likely to be constrained by a battery. A suite of applications that must be run cannot consume more total energy than is stored.
Description of Chip Morphing
However, new classes of embedded applications are emerging which not only have significant energy constraints, but also require considerable computational resources. Devices such as space rovers, cell phones, automotive control systems, and portable consumer electronics all require or can benefit from high-performance processors. The future generations of such devices should continue this trend.Processors for these devices must be able to deliver high performance with low energy dissipation. Additionally, these devices evidence large fluctuations in their performance requirements. Often a device will have very low performance demands for the bulk of its operation, but will experience periodic or asynchronous "spikes" when high-performance is needed to meet a deadline or handle some interrupt event.These devices not only require a fundamental improvement in the performance power tradeoff, but also necessitate a processor which can dynamically adjust its performance and power characteristics to provide the tradeoff which best fits the system requirements at that time.
1.2. Fast, Powerful but Cheap, and Lots of Control
These motivations point to three major objectives for a power conscious embedded processor. Such a processor must be capable of high performance, must consume low amounts of power, and must be able to adapt to changing performance and power requirements at runtime.
The objective of this seminar is to define a micro-architecture which can exhibit low power consumption without sacrificing high performance. This will require a fundamental shift to the power-performance curve presented by traditional microprocessors. Additionally, the processor design must be flexible and reconfigurable at run-time so that it may present a series of configurations corresponding to different tradeoffs between performance and power consumption.
1.3. MORPH
These objectives and motivations were identified during the MORPH project, a part of the Power Aware Computing / Communication (PACC) initiative. In addition to exploring several mechanisms to fundamentally improve performance, the MORPH project brought forth the idea of "gear shifting" as an analogy for run-time reconfiguration.Realizing that real world applications vary their performance requirements dramatically over time, a major goal of the project was to design microarchitectures which could adjust to provide the minimal required performance at the lowest energy cost. The MORPH project explored a number of microarchitectural techniques to achieve this goal, such as morphable cache hierarchies and exploiting bit-slice inactivity.One technique, multi-cluster architectures, is the direct predecessor of this work. In addition to microarchitectural changes, MORPH also conducted a survey of realistic embedded applications which may be power constrained. Also, design implications of a power aware runtime system were explored.
Chip Morphing
abstract : seminar Energy performance compromise: Engineering is a review of compromise. In computer engineering trade-off has always been between the performance measured in instructions per second, and the price. With the manufacturing technology, the price is closely related to the size of the chip and the number of transistors. With the emergence of embedded systems, a new equilibrium has been focused on the design. This new balance between performance and power or energy consumption. The requirements for computing the embedded systems have generally been more modest, and therefore the power output of compromises tend to be a balancing of power. "High Performance" and "energy efficiency" has been generally accepted concepts.Morph: Objectives and rationale of the project highlighted Morph, a part of the Power Aware Computing / Communication (parcels) initiative. In addition, several mechanisms to improve performance substantially, Morph project gave birth to the notion of 'changing gear', as an analogy, run time of reorganization. Morph project was to study a series of micro-architecture techniques for achieving this, as the morphable cache hierarchies and exploit the bit-slice of inactivity. One technique, multi-cluster architectures, has a direct predecessor of this work. In addition, micro-architectural changes that took place Morph realistic embedded applications, which may have the power to restrict. Also impact the design of power system is designed to run knowledge.
Because these embedded applications show large fluctuations in their performance requirements, the tradeoff between performance and power can change. Thus, we need an additional metric for when power consumption is less important than performance, such as ’standby’ modes found in many portable telecommunications devices. EPC provides such a metric, as it discards performance concerns and allows focus just on the energy consumed over time.
The Multi-Cluster Micro Architecture
In both cases, a relatively conventional shared fetch and decode unit fetches blocks of instructions, and determines what class of instructions they are (any branch prediction is done here). The differences between the two begin here, however. In the conventional design, a Register Renaming unit, keeps track of the mapping between architectural registers assumed by the program and the physical registers allocated to them in the common register file. In the conventional design, the new instructions are added to a common issue window, and extracted as dependencies are solved. The single common multi-ported register file holds all the physical registers.
Summary
This paper has attempted to introduce the main concepts in the Morph project, an attempt to approach low power embedded system in a novel way - by attacking power consumption during those frequent times when less than peak performance is needed.
To get full information or details of chip morphing ppt please have a look on the pages
http://studentbank.in/report-chip-morphing--15851
http://studentbank.in/report-chip-morphing-technology
http://studentbank.in/report-chip-morphing--15851
http://studentbank.in/report-chip-morphing-technology
http://studentbank.in/report-chip-morphi...ogy?page=4
http://studentbank.in/report-chip-morphi...ogy?page=2
if you again feel trouble on chip morphing pptplease reply in that page and ask specific fields in chip morphing ppt
Abstract
Engineering is a study of tradeoffs. In computer engineering the tradeoff has traditionally been between performance, measured in instructions per second, and price. Because of fabrication technology, price is closely related to chip size and transistor count. With the emergence of embedded systems, a new tradeoff has become the focus of design.Chip Morphing.Seminar Energy performance compromise: Engineering is a review of compromise. In computer engineering trade-off has always been between the performance measured in instructions per second, and the price. With the manufacturing technology, the price is closely related to the size of the chip and the number of transistors. With the emergence of embedded systems, a new equilibrium has been focused on the design. This new balance between performance and power or energy consumption. The requirements for computing the embedded systems have generally been more modest, and therefore the power output of compromises tend to be a balancing of power. "High Performance" and "energy efficiency" has been generally accepted concepts.Morph: Objectives and rationale of the project highlighted Morph, a part of the Power Aware Computing / Communication (parcels) initiative. In addition, several mechanisms to improve performance substantially, Morph project gave birth to the notion of 'changing gear', as an analogy, run time of reorganization. Morph project was to study a series of micro-architecture techniques for achieving this, as the morphable cache hierarchies and exploit the bit-slice of inactivity. One technique, multi-cluster architectures, has a direct predecessor of this work. In addition, micro-architectural changes that took place Morph realistic embedded applications, which may have the power to restrict. Also impact the design of power system is designed to run knowledge. This new tradeoff is between performance and power or energy consumption. The computational requirements of early embedded systems were generally more modest, and so the performance-power tradeoff tended to be weighted towards power. "High performance" and "energy efficient" were generally opposing concepts.
Introduction
Engineering is a study of tradeoffs. In computer engineering the tradeoff has traditionally been between performance, measured in instructions per second, and price. Because of fabrication technology, price is closely related to chip size and transistor count. With the emergence of embedded systems, a new tradeoff has become the focus of design. This new tradeoff is between performance and power or energy consumption. The computational requirements of early embedded systems were generally more modest, and so the performance-power tradeoff tended to be weighted towards power. “High performance” and “energy efficient” were generally opposing concepts. However, new classes of embedded applications are emerging which not only have significant energy constraints, but also require considerable computational resources. Devices such as space rovers, cell phones, automotive control systems, and portable consumer electronics all require or can benefit from high-performance processors. The future generations of such devices should continue this trend.
Challenges
Traditionally, performance has been improved by increasing the complexity of a micro-architecture. Unfortunately, power reduction has traditionally been accomplished by reducing processor complexity. Resolving these opposing demands is the primary challenge for low power high performance architectures.This growth in processor complexity is clearly demonstrated by the growth in the number of transistors in a processor. This complexity has taken many forms, such as multiple levels of cache, multiple functional units, and out of order execution. Though these techniques increase performance, they expend energy and experience diminishing returns. Indeed, it would appear that complex superscalar designs inherently contain too much overhead to be energy efficient.
IPC, EPI and EPC
Three key ratios are the focus to high-performance and low-power processor design: instructions per cycle (IPC), energy per instruction (EPI), and energy per cycle (EPC). These metrics can determine if a processor can provide high-performance, if it can do so in a power efficient manner, and if it dissipates little power even when high-performance is not required.IPC is the first level estimate of architectural speed. If a processor does not contain any features which would inherently limit the clock speed, IPC can provide a good estimate of actual performance. If power consumption were not an issue, then IPC would be the primary metric. EPI gives the most direct measure of energy efficiency. For embedded applications, energy measurement is generally more useful than power estimation because embedded applications are more likely to be constrained by a battery. A suite of applications that must be run cannot consume more total energy than is stored.
Description of Chip Morphing
However, new classes of embedded applications are emerging which not only have significant energy constraints, but also require considerable computational resources. Devices such as space rovers, cell phones, automotive control systems, and portable consumer electronics all require or can benefit from high-performance processors. The future generations of such devices should continue this trend.Processors for these devices must be able to deliver high performance with low energy dissipation. Additionally, these devices evidence large fluctuations in their performance requirements. Often a device will have very low performance demands for the bulk of its operation, but will experience periodic or asynchronous "spikes" when high-performance is needed to meet a deadline or handle some interrupt event.These devices not only require a fundamental improvement in the performance power tradeoff, but also necessitate a processor which can dynamically adjust its performance and power characteristics to provide the tradeoff which best fits the system requirements at that time.
1.2. Fast, Powerful but Cheap, and Lots of Control
These motivations point to three major objectives for a power conscious embedded processor. Such a processor must be capable of high performance, must consume low amounts of power, and must be able to adapt to changing performance and power requirements at runtime.
The objective of this seminar is to define a micro-architecture which can exhibit low power consumption without sacrificing high performance. This will require a fundamental shift to the power-performance curve presented by traditional microprocessors. Additionally, the processor design must be flexible and reconfigurable at run-time so that it may present a series of configurations corresponding to different tradeoffs between performance and power consumption.
1.3. MORPH
These objectives and motivations were identified during the MORPH project, a part of the Power Aware Computing / Communication (PACC) initiative. In addition to exploring several mechanisms to fundamentally improve performance, the MORPH project brought forth the idea of "gear shifting" as an analogy for run-time reconfiguration.Realizing that real world applications vary their performance requirements dramatically over time, a major goal of the project was to design microarchitectures which could adjust to provide the minimal required performance at the lowest energy cost. The MORPH project explored a number of microarchitectural techniques to achieve this goal, such as morphable cache hierarchies and exploiting bit-slice inactivity.One technique, multi-cluster architectures, is the direct predecessor of this work. In addition to microarchitectural changes, MORPH also conducted a survey of realistic embedded applications which may be power constrained. Also, design implications of a power aware runtime system were explored.
Chip Morphing
abstract : seminar Energy performance compromise: Engineering is a review of compromise. In computer engineering trade-off has always been between the performance measured in instructions per second, and the price. With the manufacturing technology, the price is closely related to the size of the chip and the number of transistors. With the emergence of embedded systems, a new equilibrium has been focused on the design. This new balance between performance and power or energy consumption. The requirements for computing the embedded systems have generally been more modest, and therefore the power output of compromises tend to be a balancing of power. "High Performance" and "energy efficiency" has been generally accepted concepts.Morph: Objectives and rationale of the project highlighted Morph, a part of the Power Aware Computing / Communication (parcels) initiative. In addition, several mechanisms to improve performance substantially, Morph project gave birth to the notion of 'changing gear', as an analogy, run time of reorganization. Morph project was to study a series of micro-architecture techniques for achieving this, as the morphable cache hierarchies and exploit the bit-slice of inactivity. One technique, multi-cluster architectures, has a direct predecessor of this work. In addition, micro-architectural changes that took place Morph realistic embedded applications, which may have the power to restrict. Also impact the design of power system is designed to run knowledge.
Because these embedded applications show large fluctuations in their performance requirements, the tradeoff between performance and power can change. Thus, we need an additional metric for when power consumption is less important than performance, such as ’standby’ modes found in many portable telecommunications devices. EPC provides such a metric, as it discards performance concerns and allows focus just on the energy consumed over time.
The Multi-Cluster Micro Architecture
In both cases, a relatively conventional shared fetch and decode unit fetches blocks of instructions, and determines what class of instructions they are (any branch prediction is done here). The differences between the two begin here, however. In the conventional design, a Register Renaming unit, keeps track of the mapping between architectural registers assumed by the program and the physical registers allocated to them in the common register file. In the conventional design, the new instructions are added to a common issue window, and extracted as dependencies are solved. The single common multi-ported register file holds all the physical registers.
Summary
This paper has attempted to introduce the main concepts in the Morph project, an attempt to approach low power embedded system in a novel way - by attacking power consumption during those frequent times when less than peak performance is needed.
To get full information or details of chip morphing ppt please have a look on the pages
http://studentbank.in/report-chip-morphing--15851
http://studentbank.in/report-chip-morphing-technology
http://studentbank.in/report-chip-morphing--15851
http://studentbank.in/report-chip-morphing-technology
http://studentbank.in/report-chip-morphi...ogy?page=4
http://studentbank.in/report-chip-morphi...ogy?page=2
if you again feel trouble on chip morphing pptplease reply in that page and ask specific fields in chip morphing ppt
02-09-2015, 07:06 AM
sir free send me chip morphing ppt and documentation for my gmail (bhavanidarapu[at]gmail.com)in web set not opening any one can send me
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