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1.Introduction
 A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself dynamically.
 This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time.
 Reconfigurable processor chip usually contains several parallel processing computational units known as functional blocks.
 While reconfiguring the chip, the connections inside the functional blocks and the connections in between the functional blocks are changing,
that means when a particular software is loaded the present hardware design is erased and a new hardware design is generated by making a particular number of connections active while making others idle.
 This will define the optimum hardware configuration for that particular software.
 It takes just 20 microseconds to reconfigure the entire processing array.
 Reconfigurable processors are currently available from Chameleon Systems, Billions of Operations (BOPS), and PACT (Parallel Array Computing Technology).
 Among those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves.
2.Multifunction Implementation
 In a conventional ASIC or FPGA, multiple algorithms are implemented as separate hardware modules. Four algorithms would divide the chip into four functional areas.
 With Reconfigurable Technology, the four algorithms are loaded into the entire reconfigurable Fabric one at a time. First, the entire Fabric is dedicated to algorithm 1; during this processing time, algorithm 2 is loaded into the background place. In a single clock cycle, the entire Fabric is swapped to algorithm 2; during this processing time, algorithm 3 is loaded into the background plane. The entire reconfigurable fabric is dedicated to just one algorithm at a time.
 So finally the result is: much higher performance, lower cost and lower power consumption
3.The General Architecture Of Reconfigurable Processor
 Machine design supposes that some pins are considered as the configuration inputs and another as data or control inputs and outputs.
 A new chip must inside determine the set of the function blocks (FB), which are used to construct the circuit, rules of their interconnections and ways of the input/output connections.
 The most important parts are the logic circuits, which configure function blocks according to data in the configuration memory.
 The various possible connections between functional blocks are encoded to bits known as Configuration bits. Resulting configuration stream is downloaded into configuration memory through configuration inputs.
Thus, a new Reconfigurable machine is established.
4.Architecture
Components:
 32-bit Risc ARC processor @125MHz
 64 bit memory controller
 32 bit PCI controller
 reconfigurable processing fabric (RPF)
 high speed system bus
 programmable I/O (160 pins)
 DMA Subsystem
 Configuration Subsystem
5.Reconfigurable Processing Fabric(RPF)
 The Fabric provides unmatched algorithmic computation power to Chameleon Chip. It consists of 84,32-bit Data path Units and 24, 16×24-bit Multipliers,Operating at 125Mhz, they provide up to 3,000 16-bit Million Multiply-Accumulates Per Second and 24,000 16-bit Million Operations Per Second.
 The fabric is divided into Slices, the basic unit of reconfiguration.
The CS2112 has 4 Slices with 3 Tiles in each. Each tile can be reconfigured at runtime
Tiles contain :
 Datapath Units
 Local Store Memories
 16x24 multipliers
 Control Logic Unit
 The high-performance 32bit Data path Unit (DPU): The Tile includes seven Data path Units. The DPU is a data processing module that directly supports all C and Verilog operations.
6.Programmable I/O
 RCP includes banks of Programmable I/O (PIO) pins which provide tremendous bandwidth.
 Each PIO bank of 40 PIO pins delivers 0.5 GBytes/sec I/O bandwidth.
7.Technologies Used In Chip
1. eCONFIGURABLE™ TECHNOLOGY:
 This technology reconfigures fabric in one clock cycle and increases voice/data/video channels per chip. As mentioned earlier, each Slice can be configured independently. Loading the Background Plane from external memory requires just 3 µsec per Slice; this operation does not interfere with active processing on the Fabric. Swapping the Background Plane into the Active Plane requires just one clock cycle. with eConfigurable Technology; the four algorithms are loaded into the entire reconfigurable processing Fabric one at a time.