[attachment=10374]
INTRODUCTION
Asynchronous circuits promise a wide range of benefits, including elimination of clock distribution networks and clock skew problems, improved performance, reduced power consumption, and modularity. Nevertheless, adoption of a fully asynchronous design style for general purpose circuits has been rather limited, mainly because of the lack of supporting CADtools and methodologies. Indeed, asynchronous circuits present their own set of challenges, making the porting of design and test methods from the synchronous domain neither straightforward nor always possible. In certain control- dominated applications, however, the use of asynchronous circuits has resulted in irrefutable advantages. In this paper, we address the problem of Concurrent Error Detection (CED) in asynchronous Burst-Mode machines. A wide variety of CED methods have been developed for synchronous controllers, their asynchronous counterparts are intrinsically different, limiting the effectiveness of these methods.
DRAWBACKS OF CED METHODS
• Lack of a global clock: Clock-less operation allows a circuit and its duplicate to produce results autonomously and at their own pace. As a result, even in error-free operation, the outputs of these circuits are not always equal. Therefore, in order toavoid false alarms, a comparison synchronization method is required.•
Existence of redundant logic: Redundancy in the implementation of the circuit is necessary to ensure hazard-free operation, as required by the communication protocol between a Burst-Mode machine and its environment. As a result of redundancy, some errors cause only hazards but no functional discrepancy, so they cannot be detected by comparison. Therefore, in order to monitor the correct interaction of the circuit and its environment, a hazard-detection method is also required.
SOLUTIONS
In short, remedial action in the form of additional hardware needs to be taken. To address the first issue, we propose a comparison synchronization method which utilizes control information inherent to the operation of asynchronous Burst-Mode controllers. To address the second issue, we propose the addition of hazard detection circuitry to the output and state bits of the original circuit.
MAIN CED METHODS
1) Duplication-basedCED: It is enhanced to guarantee detection of all functional errors and hazards in asynchronous Burst- Mode machines
.2) Transition-Triggered CED:This method reduces the overhead incurred by the enhanced duplication described above. More specifically, our method uses a transition prediction function which is derived from the functionality of the asynchronous Burst-Mode machine. In conjunction with the comparison synchronizer, this function eliminates the need for a hazard-free duplicate and is used as a less expensive method to perform hazard detection.
ASYNCHRONOUS BURST MODE MACHINES
Burst-Mode machines constitute a class of Huffman circuits, which is widely used for designing and implementing asynchronous controllers.Huffman circuits consist of a set of combinational functions, computing the next state and output of the circuit, and a set of feedback lines, storing the state of the circuit. No clock and no state registers are used in these circuits, however, delay elements are often added to eliminate essential hazards1 . Given the absence of a global clock, communication protocols are needed to ensure the correct interaction of an asynchronous circuit and its environment. These protocols define the properties of the stimuli that the environment is allowed to provide to the circuit, as well as the properties of the responses that the circuit will generate. Based on these protocols, several classes of circuits are distinguished. The key aspect of the protocol used in Burst-Mode machines, as indicated by their name, is that the interaction of the circuit and its environment happens in Bursts. An input burst is defined as a set of bit changes in one or more inputs of the circuit, which are allowed to occur in any order and without any constraint in their relative time of arrival. Once an input burst is complete, and only then, the circuit responds through a hazard-free state and output change to the environment. We emphasize the protocol requirement for hazard-free state and output changes. Since no clock is used, synchronization between the circuit and its environment is based on the fact that any change in the state or output of the circuit signifies completion of an evaluation cycle. Therefore, all hazards should be eliminated to ensure correct circuit functionality and interaction with its environment.In order to implement a circuit that complies to the aforementioned communication protocol, two features are added during the synthesis process. First, in order to make the functionality of the circuit critical-race2 free, dichotomies are added to constrain the binary state encoding of the circuit. Consequently, the resulting state codes ensure that a transition between two states never reaches a transient state with a different destination state for the current input. Second, to make the next state and output functions hazard-free, redundant implicants are added to their implementation. The popularity of Burst- Mode machines owes itself in part to the extensive research efforts that have been invested in methods and tools for automating their design . For the purpose of this work, we used a comprehensive asynchronous Burst-Mode logic synthesis package called MINIMALIST . The above constraints, along with several optimization algorithms are incorporated in MINIMALIST, yielding a minimal hazard-free logic implementation.
EXAMPLE
An asynchronous Burst-Mode machine is described using a state transition table such as the one shown in Fig. 2. The rows in the table correspond to the current symbolic state, the columns correspond to the inputs and the entry indicates the next state and the outputs. For example, if the circuit is in state S0, an input-burst of 1010 will cause a transition to state S2 and will generate an output of 00. Let us now assume that the next input burst is 1001, i.e. input c is lowered and input d is raised, and that c is lowered first and then d is raised, i.e. 1001 → 1000 → 1001. The circuit responds only after the input burst is complete, so between the time that c is lowered and the time that d is raised, the next state and output function do not change. Once the input burst is complete, the circuit will make a transition to state S0 and will compute the output, which in this case remains the same, 00. Depending on the encoding of the states, a critical-race may occur during this transition. For example, if the states are encoded as S0 = 00, S1 = 01 and S2 = 11, then the transition from S2 to S0 may go through a transient state of 01, which is the state encoding of S1. In combination with the current input burst of 1001, this will produce a next state of S1 and an output of 10, both of which are incorrect.Thus, this state encoding would be invalid for the circuit. A dash in a table entry signifies that the corresponding combination of current state and input is not permitted by the communication protocol between the circuit and the environment. For example, if the circuit is in state S1, an inputburst of 0010 is not allowed to occur. The synthesis process of MINIMALIST starts by performing state minimization on the symbolic state transition table, constrained such that the reduced state transition table has a hazard-free logic implementation . In the example of Fig. 2, the state transition table is already minimal. Next, dichotomies are added to ensure a critical- race free state encoding. Solving the dichotomies results in the state encoding S0 = 00, S1 = 01, and S2 = 10 for the example circuit and the symbolic states are replaced by their binary value