VHDL

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Introduction to VHDL :
VHDL is a hardware description language for modeling digital systems. In many respects, it is similar to a regular computer programming language such as C++. For example, it has constructs for variable assignments, conditional statements, loops, and functions, just to name a few. In a computer programming language, a compiler is used to translate the high-level source code to machine code.

In VHDL, however, a synthesizer is used to translate the source code to a description of the actual hardware circuit that implements the code. From this description, which we call a net list, the actual physical digital device that realizes the source code can be made automatically. Accurate functional and timing simulation of the code is also possible to test the correctness of the circuit.

Using VHDL to model a digital system can be done at different levels of abstraction, ranging from the structural or gate level to the behavioral or algorithmic level. At the structural level, we specify the components needed in the circuit and how these components are connected together.

To write VHDL code at this level, you must manually design the circuit first. This is analogous to writing programs in machine language.


Syntax for dataflow model:
ARCHITECTURE architecture-name OF entity-name IS
signal-declarations;
BEGIN
concurrent-statements;
END architecture-name;
The concurrent-statements are executed concurrently.
Example:
ARCHITECTURE Siren_Dataflow OF Siren IS
SIGNAL term_1: BIT;
BEGIN
term_1 <= D OR V;
S <= term_1 AND M;
END Siren_Dataflow;



Syntax for behavioral model:
ARCHITECTURE architecture-name OF entity-name IS
signal-declarations;
function-definitions;
procedure-definitions;
BEGIN
PROCESS-blocks;
concurrent-statements;
END architecture-name;
Statements within the process-block are executed sequentially. However, the process-block itself is a concurrent statement.