09-05-2011, 09:40 AM
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Introduction
The project "Speed detection using microcontroller" throws light on the concept of measuring speed in automobiles or other related equipment and displaying it suitably. The speed measurement is done with the help of a microcontroller and speed display is done on LCD. The microcontroller used in this project PIC 16F73. It is programmed so as to count interrupts. The interrupt is provided using a comparator. The output of comparator is controlled by LDR, which is illuminated by a high intensity LED. This arrangement of LED and LDR is placed on the side of wheel or the rotating part, of which speed is measured. The interrupt generated is counted by the microcontroller and speed is displayed in LCD. This is a simple method of speed measurement.
How Electronic Tachometers Work
The operation of an electronic tachometer is fairly simple. Every time a spark plug fires, the ignition system triggers a voltage pulse at the output of the tachometer electronics. The tachometer’s electromechanical part, which is simply a kind of meter movement, responds to the average voltage of the series of pulses. It is possible to show that the average voltage of the pulse “train” is proportional to engine speed.
Figure 1 shows the pulse train that we need to generate. The pulses are rectangular; that is, each pulse turns on suddenly and its voltage stays constant during the lifetime of the pulse1. The pulse length, T, stays constant as engine speed varies. As speed increases, the time between pulses, Tr, decreases, so the average voltage of the pulse train, the voltage you would measure with a dc voltmeter, increases. Luckily, the average voltage turns out to be
1. Rectangular pulses actually are not essential. As long as the pulses are identical, and the shape does not vary with their rate, everything will be OK. Rectangular pulses are very easy to generate, however, so there is no real advantage to allowing nonrectangular pulses. Note that eq.
(1) applies only to rectangular pulses.
Figure 1 Pulse train generated by the electronics and applied to the tachometer’s electrical movement. T proportional to engine speed. Since the pulses are triggered off the coil voltage, and the ignition system fires twice per revolution in a four-cylinder engine, the pulse rate (the number of pulses per minute) is twice the engine speed.
A little algebra gives the following equation for the average voltage, Vav, of the pulse train as a function of the pulse parameters:
Where C is the number of cylinders of the car, Vm is the pulse voltage, T is the pulse length in seconds, and R is the engine speed in RPM. Clearly, there are some limits to these values. The pulses cannot run together, so, at the highest engine speed, T must be somewhat less than Tr. Additionally, to operate properly, the integrated circuit used to generate the pulses (an NE555
timer), needs some time between pulses to catch its electronic breath. Thus, T probably should be about half of Tr at the highest engine speed. Finally, the pulse voltage, Vm, is limited by the NE555 to a value a few tenths of a volt below the circuit’s dc operating voltage.
Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
– 16K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 1K Byte Internal SRAM
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
• I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V for ATmega16L
– 4.5 - 5.5V for ATmega16
• Speed Grades
– 0 - 8 MHz for ATmega16L
– 0 - 16 MHz for ATmega16
• Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L
– Active: 1.1 mA
– Idle Mode: 0.35 mA
– Power-down Mode: < 1 μA
I/O Ports
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in.
Analog To Digital Converter
The ATmega16 features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows 8 single-ended voltage inputs constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND). The device also supports 16 differential voltage input combinations. Two of the differential inputs (ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage before the A/D conversion. Seven differential analog input channels share a common negative terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can be expected. The ADC contains a Sample and Hold circuit which ensures that the input voltage to the
ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 98. The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±0.3 V from VCC. See the paragraph “ADC Noise Canceler” on page 213 on how to connect this pin. Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance.
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel and differential gain are selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as positive and negative inputs to the differential gain amplifier. If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input channel pair by the selected gain factor. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
