11-05-2011, 10:39 AM
Presented by,
Nitin Bhaskar
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ARM 11 MPCore
What is ARM?
Advanced RISC Machine
32-bit processor with 16-bit & 8-bit modes
Low Power Consumption
Low latency input/output (interrupt) handling
High Code Density – Thumb mode
Seven modes of operations
ARM11 MPCore
ARM11 MPCore (Contd.)
Up to 4 CPUs implementing ARM v6
Snoop Control Unit – Cache Coherency
Distributed Interrupt Controller
Private Timer and Private Watchdog for each CPU
AXI high speed Advanced Microprocessor Bus Architecture (AMBA) level two interfaces
ARM11 CPU Pipeline Stages
ARMv6 Registers
7 modes of operation (usr, fiq, irq, svc, abt, sys, und)
Register Banks and Link Register
Total of 37 registers, all are 32-bit registers
1 dedicated program counter
5 SPSR registers
1 CPSR registers
1 stack pointer(r13) and 1 page link registers(r14) for each mode.
The ARM Register Set
Program Status Registers
Condition code flags
N = Negative result from ALU
Z = Zero result from ALU
C = ALU operation Carried out
V = ALU operation oVerflowed
Sticky Overflow flag - Q flag
Indicates if saturation has occurred
J bit
J = 1: Processor in Jazelle state
Interrupt Disable bits.
I = 1: Disables the IRQ.
F = 1: Disables the FIQ.
T Bit
Architecture xT only
T = 0: Processor in ARM state
T = 1: Processor in Thumb state
Mode bits
Specify the processor mode
Branch Prediction
Dynamic branch prediction
128-entry Branch target Address Cache (BTAC)
2-bit prediction history bits
Static branch prediction
Used when BTAC entry not available
Configured in hardware to take branches with negative offsets, and not taken for positive offset.
This would help in loop performance.
Cache
32-bit interface to the instruction cache and 64-bit interface to the data cache
Hardware support for data cache coherency
The instruction and data cache can be independently configured during synthesis to sizes between 16KB and 64KB.
SIMD Capabilities
Vector Floating-Point coprocessor performs operations on 8 single-precision or 4 double precision values simultaneously, in parallel with CPU
Dedicated interface to main processor
Results of compare instructions are stored in CPU status register.
Vector Floating Point coprocessor
VFP does the floating point operations.
VFP has 3 separate instruction pipeline.
Each pipeline shares decode and issue stages, but otherwise works independently and in parallel
Multiply and Accumulate (FMAC) pipeline has 7 execution stages
Divide and Square root (DS) pipeline has 4 execution stages
Load/Store (LS) pipeline has 1 execution and 2 memory access stages, and is responsible for communicating with the main processor
ARMv6 – the Performance
Media processing extensions
2x faster MPEG4 encode/decode
2x faster audio DSP
Improved cache architecture
Physically addressed caches
Reduced overhead in context switches
Improved exception and interrupt handling
Important for improving performance in real-time tasks
ARM Architecture Feature Comparisons
Applications
Its media processing capability, and low power characteristics make it particularly suited to wireless and consumer applications.
Mobile phones, Handhelds, tablets, etc.
PC Graphics cards.
Medical instruments which requires real time image processing.
