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ARM Instruction Set
Main features of the ARM Instruction Set
* All instructions are 32 bits long.
* Most instructions execute in a single cycle.
* Every instruction can be conditionally executed.
* A load/store architecture
• Data processing instructions act only on registers
– Three operand format
– Combined ALU and shifter for high speed bit manipulation
• Specific memory access instructions with powerful auto-indexing addressing modes.
– 32 bit and 8 bit data types
 and also 16 bit data types on ARM Architecture v4.
– Flexible multiple register load and store instructions
* Instruction set extension via coprocessors
Processor Modes
* The ARM has six operating modes:
• User (unprivileged mode under which most tasks run)
• FIQ (entered when a high priority (fast) interrupt is raised)
• IRQ (entered when a low priority (normal) interrupt is raised)
• Supervisor (entered on reset and when a Software Interrupt instruction is executed)
• Abort (used to handle memory access violations)
• Undef (used to handle undefined instructions)
* ARM Architecture Version 4 adds a seventh mode:
• System (privileged mode using the same registers as user mode)
The Registers
* ARM has 37 registers in total, all of which are 32-bits long.
• 1 dedicated program counter
• 1 dedicated current program status register
• 5 dedicated saved program status registers
• 30 general purpose registers
* However these are arranged into several banks, with the accessible bank being governed by the processor mode. Each mode can access
• a particular set of r0-r12 registers
• a particular r13 (the stack pointer) and r14 (link register)
• r15 (the program counter)
• cpsr (the current program status register)
and privileged modes can also access
• a particular spsr (saved program status register)
Register Organisation
Accessing Registers using ARM Instructions
* No breakdown of currently accessible registers.
• All instructions can access r0-r14 directly.
• Most instructions also allow use of the PC.
* Specific instructions to allow access to CPSR and SPSR.
* Note : When in a privileged mode, it is also possible to load / store the (banked out) user mode registers to or from memory.
• See later for details.
The Program Status Registers (CPSR and SPSRs)
The Program Counter (R15)
* When the processor is executing in ARM state:
• All instructions are 32 bits in length
• All instructions must be word aligned
• Therefore the PC value is stored in bits [31:2] with bits [1:0] equal to zero (as instruction cannot be halfword or byte aligned).
* R14 is used as the subroutine page link register (LR) and stores the return address when Branch with Link operations are performed,
calculated from the PC.
* Thus to return from a linked branch
• MOV r15,r14
or
• MOV pc,lr

ARM Instruction Set

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ARM REGISTERS:
ARM has load-store architecture: data operands must first be loaded into the CPU, and then stored back to main memory to save the results. It has 16 general-purpose registers, r0 through r15. Except for r15, they are identical. The r15 register has the same capabilities as the other registers, but it can also be used as a program counter (PC).
The other important basic register is the current program status register (CPSR). This register is set automatically during every arithmetic, logical, or shifting operation. The top 4 bits hold the following information of that operation:
• The Negative (N) bit is set when the result is negative in two’s-complement arithmetic.
• The Zero (Z) bit is set when every bit of the result is zero.
• The Carry © bit is set when there is a carry out of the operation.
• The Overflow (V) bit is set when an arithmetic operation results in an overflow.


ARM INSTRUCTIONS:
The major assembly instructions for data operations are summarized in the annex. They allow arithmetic, logical and shift/rotate operations, as well as comparison, and data moving and loading. The shift/rotate operations are considered as additional operands to the previous operation.