Application of Logical Effort on Design of Arithmetic Blocks full report
#1

Abstract
In this paper, we review the logical effort model presented in [1]. Based on the HSPICE simulation results using 0.18/Jm, CMOS technology as applied to logic blocks used in arithmetic circuits; we analyze the efficiency of the model and also present modifications that include modeling of wire delay. We propose a new model for logical effort that will better fit the behavior of these blocks. The results are applicable for evaluation of arithmetic units as well as for development of new arithmetic algorithms. Our ultimate objective is to close the gap between arithmetic algorithms and their performance in VLSI CMOS.

Presented By:
Xiao Yan Yu*,**, Vojin G. Oklobdzija*,** * ACSEL Laboratory Electrical and Computer Engineering Department University of California, Davis
William W. Walker** **Advanced LSI Research Fujitsu Laboratory of America Sunnyvale, California

1. Introduction
Sutherland and Sproull [1] presented a simple logical effort (LE) delay model d = z(gXh + Pinv), where x is the intrinsic delay of an inverter, g is the logical effort of the gate or how well the gate drives current in compare to a minimal sized inverter, which is the ratio of the on-resistance of the gate to the on-resistance of an inverter with the same input capacitance, h is the electrical effort of the gate, which is the ratio of load capacitance to input capacitance, and zP,nv is the parasitic delay of the gate. After unnormalizing, the delay model for LE can be seen to be simply d = ?0 + R.X.Cload where to is the intrinsic delay of the gate, which is equivolent to zP^,,, R is its on-resistance value and Cioaa is the load capacitance. Table 1 provides a list of theoretical logical effort values for NAND and NOR gates assuming the optimal ratio of PMOS tran'sistor size to NMOS transistor size is 2 for an inverter.


read full report
http://citeseerx.ist.psu.edu/viewdoc/dow...1&type=pdf
Reply

Important Note..!

If you are not satisfied with above reply ,..Please

ASK HERE

So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page
Popular Searches: filesystem blocks, ppt for arithmetic and logical instructions of 8086, basic arithmetic logic program for microcontroller and microprocessor free download, power blocks, the building blocks of net, arithmetic operations in java using servlets, project report of concrete blocks,

[-]
Quick Reply
Message
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  Transparent electronics full report seminar surveyer 8 24,357 04-04-2018, 07:54 AM
Last Post: Kalyani Wadkar
  wireless charging through microwaves full report project report tiger 90 70,544 27-09-2016, 04:16 AM
Last Post: The icon
  Wireless Power Transmission via Solar Power Satellite full report project topics 32 50,218 30-03-2016, 03:27 PM
Last Post: dhanabhagya
  surge current protection using superconductors full report computer science technology 13 26,848 16-03-2016, 12:03 AM
Last Post: computer science crazy
  paper battery full report project report tiger 57 61,685 16-02-2016, 11:42 AM
Last Post: Guest
  IMOD-Interferometric modulator full report seminar presentation 3 11,363 18-07-2015, 10:14 AM
Last Post: [email protected]
  digital jewellery full report project report tiger 36 66,489 27-04-2015, 01:29 PM
Last Post: seminar report asees
  LOW POWER VLSI On CMOS full report project report tiger 15 22,193 09-12-2014, 06:31 PM
Last Post: seminar report asees
  eddy current brake full report project report tiger 24 33,404 14-09-2014, 08:27 AM
Last Post: Guest
  dense wavelength division multiplexing full report project reporter 3 4,513 16-06-2014, 07:00 PM
Last Post: seminar report asees

Forum Jump: