Abstract:
Reversible logic gates are very much in demand for the future computing technologies as they are known to producezero power dissipation under ideal conditions. This paper proposes an improved design of a multiplier usingreversible logic gates. Multipliers are very essential for the construction of various computational units of a quantumcomputer. The quantum cost of a reversible logic circuit can be minimized by reducing the number of reversiblelogic gates. For this two 4*4 reversible logic gates called a DPG gate and a BVF gate are used.
Keywords: Reversible logic circuits; quantum computing; Nanotechnology.
1. Introduction
Reversible logic has received great attention in the recent years due to their ability to reduce the powerdissipation which is the main requirement in low power VLSI design. Quantum computers are constructed usingreversible logic circuits. It has wide applications in low power CMOS and Optical information processing, DNAcomputing, quantum computation and nanotechnology. In 1960 R.Landauer demonstrated that high technologycircuits and systems constructed using irreversible hardware result in energy dissipation due to information loss [1].According to Landauer’s principle, the loss of one bit of information dissipates KTln2 joules of energy where K isthe Boltzmann’s constant and T is the absolute temperature at which the operation is performed [1]. The heatgenerated due to the loss of one bit of information is very small at room temperature but when the number of bits ismore as in the case of high speed computational works the heat dissipated by them will be so large that it affects theperformance and results in the reduction of lifetime of the components. In 1973, Bennett, showed that one can avoidKTln2 joules of energy dissipation constructing circuits using reversible logic gates [2].
2. Reversible logic gates
A reversible logic gate is an n-input n-output logic device with one-to-one mapping. This helps todetermine the outputs from the inputs and also the inputs can be uniquely recovered from the outputs. Also in thesynthesis of reversible circuits direct fan-out is not allowed as one–to-many concept is not reversible. However fanoutin reversible circuits is achieved using additional gates. A reversible circuit should be designed using minimumnumber of reversible logic gates. From the point of view of reversible circuit design, there are many parameters fordetermining the complexity and performance of circuits [3, 4 and 18].• The number of Reversible gates (N): The number of reversible gates used in circuit.• The number of constant inputs (CI): This refers to the number of inputs that are to be maintained constant ateither 0 or 1 in order to synthesize the given logical function.• The number of garbage outputs (GO): This refers to the number of unused outputs present in a reversible logiccircuit. One cannot avoid the garbage outputs as these are very essential to achieve reversibility.• Quantum cost (QC): This refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculatedknowing the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit.ISSN: 0975-5462 3838H.R.Bhagyalakshmi et. al. / International Journal of Engineering Science and TechnologyVol. 2(8), 2010, 3838-3845• Gate levels (GL): This refers to the number of levels in the circuit which are required to realize the given logicfunctions [18].Reduction of these parameters is the bulk of the work involved in designing a reversible circuit. In this paper, animproved design of reversible multiplier with respect to its previous counterparts is proposed. Multiplier circuitsplay an important role in computational operation using computers. There are many arithmetic operations which areperformed, on a computer ALU, through the use of multipliers. Design and implementation of digital circuits usingreversible logic has attracted popularity to gain entry into the future computing technology.This paper is organized as follows: Section 2 gives the brief introduction of the reversible logic gatesrequired for the present work. Section 3 describes the design of multiplier circuit and the implementation of theproposed multiplier circuit using new reversible gates. Section 4 gives the results and discussions and thecomparative study of different designs with the proposed design. Finally Section 5 concludes with a scope forfurther research.
2. Design of Reversible Multiplier
The design of the proposed multiplier uses parallel multiplier is done using two steps.Part I: Partial Product Generation (PPG)Part II: Multi-Operand Addition (MOA)The operation of a 4*4 reversible multiplier is shown in Fig 10. It consists of 16 Partial product bits of the X and Yinputs to perform 4 * 4 multiplications. However, it can extended to any other n * n reversible multiplier
3.2 Multi-operand Addition (MOA)
As proposed in [12], to implement an n operand addition circuit part a carry save adder (CSA) is used. TheCSA tree reduces the four operands to two. Thereafter, a Carry Propagating Adder (CPA) adds these two operandsand produces the final 8-bit product. The proposed four operand adder shown in Fig 13 uses DPG gate as areversible full adder and Peres gate as half adder

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