Abstract
In this paper, we propose a new transparent
Built-In Self-Diagnosis ( BISD ) method to diagnose multiple
embedded memory arrays with various sizes an parallel.
A new tmnspamnt diagnostic interface has been proposed
to perform testing in n m l mode. By tolerating redundant
read/urite/shift operations, we develop a new mamh
algorithm called TDiagRSMarch to achieve the ywls of low
hardware overhead, lower test time, and hiyh test coverage.
Experh"ea1 results demonstrate that the diagnostic eflciency
of TDiagRSMamh is independent on mewry topology,
defect-type distribution, and degree of pamllelism.
Inda Words: Memory Test, Built-In Self-Diagnosis,
II)ansparent diagnosis
I. INTRODUCTION
Because of the improvement of VLSI technologies,
many components can be fabricated into a single chip.
This induces various testing problems due to the inaccessibility
of components; especially in memory modules,
all transistors are so highly condensed that they are very
vulnerable to fabrication defects. In general, some memory
arrays are used to store some valuable data and the
correctness of these also dominate the function of chip.
For example in a superscalar CPU chip, the reorder
buffer is a set of memory arrays used to control the execution
order of instructions. Thus, the testing and diagnosis
of memory buffers are very important. However,
memory devices contained on a single chip might be defective
during the normal operation. To resolve such a
problem, an on-line repairing scheme is proposed. Thus,
a more cost-efficient solution is to use transparent diagnosis
by which memory devices on a chip is diagnosed
periodically. The basic requirement of transparent diagnosis
is that the memory contents must be restored to
the initial state such that the normal operations can be
resumed.
Historically, several papers have discussed BISD and
BISR of memory from different aspects[l][2][3][4][5][6].
All these papers perform the diagnosis in an off-line
mode. That is, the diagnosis of memory can not be performed
in the normal operation mode. Thus, we need
to stop the normal operation mode and to enter into
the diagnostic mode. To test memory in normal mode,
there are discussed in several papers [7][8][9][10][11][121
and a transparent testing concept has been proposed. In
other words, the content of memory can be recovered to
its original format after executing the testing. However,
Fig. 1. The serial interfacing technique for a memory array.
these papers do not mention about the diagnostic issue.
Most of these papers are related to the testing issue. In
[13], a software method has been proposed to diagnose
the memory in a transparent and a relocation scheme is
also presented.
Here, we develop an efficient method to concurrently
diagnose and repair spatially distributed memory modules
with different sizes. To save test data routing area,
the serial interfacing technique is used. Also, a circular
comparator is proposed to cope with the diagnosis and
identscation of defective cell. Based on this test architecture,
only a single test controller is required to sup
port the BET and BISD functions for all memory modules.
Further, only very limited number of test signals
are required to be routed on the entire chip. After investigating
the relationships between different fault types, a
parallel diagnosis method called TDiagRSMarch is pre
posed to generate test patterns and evaluate test output
responses. The TDiagRSMarch algorithm guarantee the
identification of all stuck-at, transition, coupling faults
occurring at all memory modules.


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