AMD’S BULLDOZER ARCHITECTURE
#1

[attachment=14537]
ABSTRACT
Bulldozer is the codename AMD has given to one of the next-generation CPU cores
after the K10 microarchitecture for the company's M-SPACE design methodology, with the
core specifically aimed at 10 watt to 125 watt TDP computing products.
Basically, it is a monolithic dual core building block that supports two threads of
execution and is intended for deployment in everything from mainstream clients (including
desktops and notebooks) to servers.
The bulldozer architecture has two dedicated integer cores. Each of these consist of
2 Arithmetic Logic Unit 2 AGU which together can execute 4 independent arithmetic or
memory operations per clock cycle per core. Core module of AMD bulldozer shares
portions of a traditional core—including the instruction fetch, decode, and floating-point
units and L2 cache—between two otherwise-complete processor cores. The integer core has
duplicating integer schedulers. The execution pipeline offers dedicated hardware
significantly increasing performance in multi-threaded integer applications.
CHAPTER -1
INTRODUCTION

AMD is unveiling today the new processor architecture that will be used in their
new CPUs starting in 2011. Codenamed Bulldozer, this architecture is completely different
from the current AMD64 architecture that AMD has been using since the introduction of the
very first Athlon 64 CPU back in 2003.
Bulldozer will be the first major redesign of AMD’s processor architecture since
2003, when the firm launched its Athlon 64/ Opteron (K8) processors, and will feature two
128-bit FMA-capable FPUswhich can be combined into one 256-bit FPU. This design is
accompanied by two integer cores each with 4 pipelines (the fetch/decode stage is shared).
Bulldozer will also introduce shared L2 cache in the new architecture. AMD calls this
design a "Bulldozer module". A 16-core processor design would feature eight of these
modules, but the operating system will recognize each module as two physical cores.
The module, described as two cores, can be compared to a single Intel core with HyperThreading. The difference between the two approaches is that Bulldozer provides dedicated schedulers and integer units for each thread, whereas in Intel's core each thread can access all available resources, except for the individual thread state information.
The Bulldozer architecture will inherit some features introduced with the AMD64 architecture, such as the integrated memory controller and the use of the Hyper Transport bus for communication between the CPU and the chipset.
Bulldozer is the codename for the architecture, not for a specific processor. AMD has proposed the first desktop CPUs based on the Bulldozer architecture will require a new CPU socket, called AM3+, which will also be compatible with current socket AM3 processors. Socket AM3+ CPUs, however, won’t be compatible with socket AM3 motherboards.
Reply
#2
Sir pls upload a brief description and ppt...............
Reply
#3
To get more information about the topic " AMD’S BULLDOZER ARCHITECTURE" please refer the page link below

http://studentbank.in/report-amd%E2%80%9...6#pid52016
Reply

Important Note..!

If you are not satisfied with above reply ,..Please

ASK HERE

So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page
Popular Searches: ppt on amd bulldozer, amd athlontm x2 dual core processors for notebooks, amd processor seminar report, dioloma in mechanical interview question amd answer pdf download, advantages amd disadvantages of prony brake dynamometer, how to coolect data of hdfc bank abiut recruitment amd selection, bulldozer ppt,

[-]
Quick Reply
Message
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  service oriented architecture full report project report tiger 12 14,781 27-04-2015, 01:48 PM
Last Post: seminar report asees
  Computer Architecture Requirements? shakir_ali 1 27,441 07-04-2015, 12:04 PM
Last Post: Kishore1
  Computer Architecture ACS Project? shakir_ali 0 7,529 30-10-2014, 12:01 AM
Last Post: shakir_ali
  Web Services Architecture computer topic 0 7,592 25-03-2014, 10:20 PM
Last Post: computer topic
  Java Cryptography Architecture (JCA) seminar projects crazy 1 2,583 17-12-2012, 01:51 PM
Last Post: seminar details
Lightbulb Java Cryptography Architecture (JCA) computer science crazy 1 2,637 17-12-2012, 01:51 PM
Last Post: seminar details
  GSM Architecture seminar surveyer 7 5,888 14-12-2012, 02:45 PM
Last Post: seminar details
  Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture summer project pal 3 2,942 01-12-2012, 12:40 PM
Last Post: seminar details
  8085 Microprocessor Architecture seminar class 2 4,649 23-11-2012, 01:28 PM
Last Post: seminar details
  microcontrollers based on CISC architecture. RICS stands for Reduced Instruction Set seminar surveyer 2 3,172 01-11-2012, 01:13 PM
Last Post: seminar details

Forum Jump: