24-01-2015, 02:44 AM
advantages and disadvantages of wallace tree multiplier using compressors
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advantages and disadvantages of wallace tree multiplier
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advantages and disadvantages of wallace tree multiplier using compressors
31-03-2017, 12:06 PM
Multipliers are the basic blocks of many VLSI computational units. The performance of such VLSI circuits depends on the performance of the multipliers. Therefore designing a high performance multiplier is a difficult task for VLSI designers. Wallace Tree Multiplier or Wallace Multiplier is the most popular multiplier among existing multipliers. Wallace multiplier is also known for its fast speed and low power consumption. Different techniques for designing a Wallace multiplier are available in the literature. This article includes the performance benchmark review of several Wallace multiplier architectures. The multiplication operation is an integral part of any digital system or digital computer, especially in signal processing, graphics and scientific computing. It requires more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all instructions on a typical processing unit is multiplier. The speed of the system depends to a large extent on the speed of the multiplier. This requires the need for a high speed multiplier. With the advancement in technology, several techniques have been proposed to design multipliers, which offer high speed, low power consumption and smaller area. Therefore, making them suitable for several high-speed, low-power VLSI compact implementations. This article presents a new design of a Hybrid Wallace high speed tree multiplier. Multipliers have gained significant importance with the introduction of digital computers. Multipliers are most commonly used in digital signal processing applications and microprocessor designs. In contrast to the addition and subtraction process, multipliers consume more time and more hardware resources. With recent advances in technology, a number of multiplication techniques have been implemented to meet the requirement to produce high speed, low power consumption, smaller area or a combination of them in a multiplier. Speed and area are the two main conflicting constraints. Therefore, it is the task of the designer to decide the appropriate balance in the selection of a suitable multiplication technique according to the requirements.
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