07-05-2017, 06:40 PM
what are the advantages and disadvantages of jk flipflops
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advantages and disadvantages of jk flip flop
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what are the advantages and disadvantages of jk flipflops
08-05-2017, 09:31 AM
Advantages
The advantage of J-K flip-flops that once made them popular is that for any desired output transition, one of the two inputs is a "no matter". This offers many possibilities for logical reduction.
The advantage of flip-flops D is their simplicity and the fact that the output and the input are essentially identical, except shifted in time by a clock period.
In FPGA technology, the "fabric" FPGA consists mainly of D flip-flops surrounded by programmable reference tables that provide any required combinational logic. This structure has been selected by FPGA manufacturers as a good balance between efficient resource utilization, power consumption and performance.
Disadvantages
The disadvantage of the SR flip-flop is that both inputs should not be HIGH when the clock is turned on. This is considered an invalid input condition and the resulting output is not predictable if this condition occurs.
The main difference between a JK flip-flop and a SR flip-flop is that on the JK flip-flop, both inputs can be HIGH. When inputs J and K are HIGH, output Q is switched, which means that the output alternates between HIGH and LOW. This removes the invalid condition that occurs on the flipflop SR.
The advantage of J-K flip-flops that once made them popular is that for any desired output transition, one of the two inputs is a "no matter". This offers many possibilities for logical reduction.
The advantage of flip-flops D is their simplicity and the fact that the output and the input are essentially identical, except shifted in time by a clock period.
In FPGA technology, the "fabric" FPGA consists mainly of D flip-flops surrounded by programmable reference tables that provide any required combinational logic. This structure has been selected by FPGA manufacturers as a good balance between efficient resource utilization, power consumption and performance.
Disadvantages
The disadvantage of the SR flip-flop is that both inputs should not be HIGH when the clock is turned on. This is considered an invalid input condition and the resulting output is not predictable if this condition occurs.
The main difference between a JK flip-flop and a SR flip-flop is that on the JK flip-flop, both inputs can be HIGH. When inputs J and K are HIGH, output Q is switched, which means that the output alternates between HIGH and LOW. This removes the invalid condition that occurs on the flipflop SR.
Summary
The sequential operation of the JK flip-flop is exactly the same as for the previous SR flip-flop with the same "Set" and "Reset" inputs. The difference between the two flip flops is that the "JK" flip-flop has no invalid or prohibited SR Latch input states even when S and R are both in logic "1".
The JK flip-flop is basically a closed SR flip-flop with the addition of a clock input circuit which avoids the illegal or invalid output condition that can occur when both S and R inputs are equal to the logic level "1" . Due to this additional synchronized input, a JK flip-flop has four possible input combinations, "logic 1", "logic 0", "no change" and "switch".
Both the S inputs and the R inputs of the previous SR flip-flop have been replaced by two inputs named inputs J and K, respectively, after their inventor Jack Kilby. Then this equals: J = S and K = R.
The two 2-input AND gate inputs of the locked SR flip-flop have now been replaced by two 3-input NAND gates with the third input of each gate connected to the Q and Q outputs. This SR flip-flop cross-coupling allows the Condition previously Invalid of S = "1" and R = "1" state to be used to produce a "switching action" since the two inputs are now interlaced.
If the circuit is now "SET" the J input is inhibited by the "0" state of Q through the lower NAND gate. If the circuit is "RESET" the input K is inhibited by the "0" state of Q through the upper NAND gate. Since Q and Q are always different we can use them to control the input. When both inputs J and K are equal to logic "1", the JK flip-flop changes.
Thus, the JK flip-flop is basically a feedback flip-flop SR that allows only one of its two input terminals, SET or RESET to be active at any time, thus eliminating the invalid condition previously seen in the SR flop circuit. Also when both inputs J and K are at the logic level "1" at the same time, and the clock input is pressed or "HIGH", the circuit will change from its SET state to a RESET or visa- Flip-flop JK acts more like a T-type flip-flop when both terminals are "HIGH".
Although this circuit is an improvement on the synchronized SR flip-flop, it still suffers from so-called "race" timing problems if the Q output changes state before the timing pulse of the clock input has time to shut down. To avoid this, the timing pulse period (T) must be kept as short as possible (high frequency). As this is sometimes not possible with the modern TTL IC, the greatly improved Master-Slave JK Flip-flop was developed.
The M-S JK flip-flop eliminates all timing problems by using two SR flip-flops connected together in a series configuration. A flip-flop acts as the "Master" circuit, which activates on the leading edge of the clock pulse while the other acts as the "Slave" circuit, which activates on the falling edge of the clock pulse. This results in the two sections, the master section and the slave section being enabled during opposing half-cycles of the clock signal.
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