ABSTRACT
This paper describes the implementation of a low cost PC - based logic system suitable for either
small scale chip or printed circuit board testing. The system incorporates a flexible graphical user interface
(GUI) which permits users with little or no programming expertise to generate tests and operate the system
quickly and efficiently. System cost is of the order of £1,000 which makes it very attractive to SME's.
1 INTRODUCTION
In any manufacturing industry there are continuous efforts to effect cost reductions, upgrade quality
and improve overall efficiencies. In the electronics industry, with the dramatic increase in circuit complexity
and the need for higher levels of reliability, a major contributory cost of any product can be in the testing.
However, in the real world we have to recognise that no process can be perfect, so that testing, and in
particular, automatic testing, will be an essential part of production for the foreseeable future.
In this paper the development of a prototype digital functional IC tester is described. The test system
has been designed so that the end user has total control over how testing of IC's is to be carried out. The
end user will have the ability to change or redefine pin connections of any IC within the data bank, alter test
vectors previously defined, specify the master clock period, carry out simulated testing, check the contents
of the data base and obtain information on the PC 8255 I/O Card set-up.
The test system has been developed to allow for a more detailed examination of how IC's operate for
particular functional tests. To date all test systems on the market (except for extremely expensive ATE)
only inform the end user whether the device under test (DUT) has passed or failed their own predefined
test. This gap in the market has called for this prototype tester.
One objective of improved test equipment would be an increase in throughput by providing a better
test. However this prototype test system has not been designed to carry out exhaustive tests. The
application of 2n test vectors to a device with n inputs is effective if n was small. However because the
number of tests, 2n , grows exponentially with n, the number of tests required increases rapidly. For n
inputs the truth table contains 2n lines; if we work through the table at 1 test/ms, this would take 18 min
for n = 30, 13 days for n = 40 , & 36 years for n = 50. Quiet obviously this method of exhaustive testing is
unacceptable for end of line testing. An alternative approach is based on the observation that ,' in a device,
any particular input test vector will usually cover a significant number of faults' ref[1]. Any random
selection of tests of reasonable size, therefore can be expected to achieve reasonable fault coverage.
Strunz R, Toal D, McGowan C.
R.D Eldner ref[2] advocated creating specific tests for faults most likely to occur . This method has become
the standard approach to developing tests for digital logic IC's.
An analysis of statistical methods that estimate the quality of a test set based on probabilities of
detecting faults with random vectors is beyond the scope of this paper. For further information relating to
this area refer to Abramovici et al, ref[3].

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