05-03-2011, 03:43 PM
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A Low-Power Small-Area 1-bit Full Adder Cell in a 0.35μm CMOS Technology for Biomedical Oriented System-on-Chip Applications
[b]Abstract:-[/b]
In this paper a low-power small-area 1-bit CMOSbased adder cell is being introduced. It needs only 14 transistors and relies on low-power XOR/XNOR cells, transmission function logic and pass-gate logic cells to compute the sum and carry-out bits with rail-to-rail output swing. The proposed adder cell, which has been designed and laid out according to the layout requirements of a 0.35 μm 3.30 V CMOS technology, consumes 45% less power and occupies 47% less area than the 28-transistor standard cell provided by the technology supplier, making it attractive for being used in low-power applications, such as in a Biomedical-oriented system-on-chip design.
I. INTRODUCTION
The demand of high-performance low-power microelectronic-based circuits for bio-medical applications grows continuously in order to boost the development of innovative medical devices and medical technologies, which are actually indispensable for delivering high-quality healthcare [1]. In contrast to that proposed in [2], a biomedical-oriented system-on-chip (SoC) that encapsulates a number of subsystems (e.g. analogue front-ends, analogue-to-digital converters, dedicated digital filters, a digital signal processor and related memory) for the acquisition, digitization and processing of biosignals (e.g. electrocardiographic signals) will help develop less power consuming (i.e. battery powered), more compact and more versatile systems,. Consequently, low power design and small-area circuits are mandatory for the design of such SoC.
Because addition operations are extensively used in digital signal processing, a low-power small-area 14-transistor 1-bit adder cell with rail-to-rail output swing is presented. The cell is designed and laid out in a 0.35μm 3.30V CMOS technology and is meant to replace the 28-transistor 1-bit standard CMOS adder [3] provided by the technology supplier. Several few-transistor-count adder cells have been proposed in the literature [4]-[5], but have the disadvantage of demanding more than 14 transistors, which negatively impact the area of the cell, or of not producing full swing output signals, which worsens the noise margin and the driving capability of the cell, and makes subsequent buffering stages dissipate considerable amounts of power.
This paper is organized as follows: Section II addresses the principle of operation of the proposed 14-transistor adder cell; functional verification of the proposed 1-bit adder, including a comparison against the cells reported in [4]-[5] and the 28- transistor standard CMOS adder, is done through simulations, the results of which are discussed in Section III; in Section IV the design flow for the creation of the customized digital cell that can be used in the computer-assisted synthesis, and floor planning, placement and routing (FPR) flows of digital designs is reviewed; conclusions are given in Section V This paper complements also the work presented in [6] about low power analogue-to-digital conversion for SoC applications.
II. PRINCIPLE OF OPERATION OF THE PROPOSED 1-BIT ADDER
A 1-bit adder cell is a digital circuit that takes three 1-bit inputs A, B, and Cin, to produce two output bits S and Cout, according to the following Boolean equations:
