Abstract
This paper presents circuit design of a low-powerdelay buffer. The proposed delay buffer uses several new techniquesto reduce its power consumption. Since delay buffers areaccessed sequentially, it adopts a ring-counter addressing scheme.In the ring counter, double-edge-triggered (DET) flip-flops areutilized to reduce the operating frequency by half and the C-elementgated-clock strategy is proposed. A novel gated-clock-drivertree is then applied to further reduce the activity along the clockdistribution network. Moreover, the gated-driver-tree idea is alsoemployed in the input and output ports of the memory blockto decrease their loading, thus saving even more power. Bothsimulation results and experimental results show great improvementin power consumption. A 256 8 delay buffer is fabricatedand verified in 0.18 m CMOS technology and it dissipates only2.56 mW when operating at 135 MHz from 1.8-V supply voltage.
Index Terms—C-element, delay buffer, first-in–first-out (FIFO),gated-clock, ring-counter.
I. INTRODUCTION
P ORTABLE multimedia and communication devices haveexperienced explosive growth recently. Longer battery lifeis one of the crucial factors in the widespread success of theseproducts. As such, low-power circuit design for multimedia andwireless communication applications has become very important.In many such products, delay buffers (line buffers, delaylines) make up a significant portion of their circuits [1]–[3]. Suchserial access memory is needed in temporary storage of signalsthat are being processed, e.g., delay of one line of video signals,delay of signals within a fast Fourier transform (FFT) architectures[4], and delay of signals in a delay correlator [2]. Currently,most circuits adopt static random access memory (SRAM) plussome control/addressing logic to implement delay buffers. Forsmaller-length delay buffers, shift register can be used instead.The former approach is convenient since SRAM compilers arereadily available and they are optimized to generate memorymodules with low power consumption and high operation speedwith a compact cell size. The latter approach is also convenientsince shift register can be easily synthesized, though it mayconsume much power due to unnecessary data movement.Previously, a simplified and thus lower-power sequential addressingscheme for SRAM application in delay buffers is proposedin [5]. A ring counter is used to point to the target words to be written-in and read-out. Since the ring counter is made upof an array of D-type flip-flops (DFFs) triggered by a globalclock signal and all except one DFFs have a value of “0,” itis possible to disable the clock signal to most DFFs. Such agated-clock ring counter is implemented in [6] to compose alow-power first-in–first-out (FIFO) memory.In this paper, we propose to use double-edge-triggered (DET)flip-flops instead of traditional DFFs in the ring counter to halvethe operating clock frequency. A novel approach using the C-elementsinstead of the R–S flip-flops in the control logic for generatingthe clock-gating signals is adopted to avoid increasingthe loading of the global clock signal. In addition to gating theclock signal going to the DET flip-flops in the ring counter, wealso proposed to gate the drivers in the clock tree. The techniquewill greatly decrease the loading on distribution networkof the clock signal for the ring counter and thus the overall powerconsumption. The same technique is applied to the input driverand output driver of the memory part in the delay buffer. In adelay buffer based on the SRAM cell array such as the one in[6], the read/write circuitry is through the bit lines that work asdata buses. In the proposed new delay buffer, we use a tree hierarchyfor the read/write circuitry of the memory module. For thewrite circuitry, in each level of the driver tree, only one driveralong the path leading to the addressed memory word is activated.Similarly, a tree of multiplexers and gated drivers comprisethe read circuitry for the proposed delay buffer. Simulationresults show the effectiveness of the above techniques inpower reduction. As an example, a 256 8 delay buffer chipis designed and fabricated. Measured results indicate its muchbetter power performance than the same-size delay buffer basedon existing commercial SRAM.The rest of this paper is organized as follows. Section IIfirst introduces the conventional architecture for implementingdelay buffers. Next, the proposed delay buffer using the newring counter and gated driver trees for the read and writecircuits of the memory module is described in Section III.Section IV then presents experimental results of the new delaybuffer. Also, comparison in power and area of the new delaybuffer with conventional SRAM-based delay buffers are given.Section V then concludes this paper.
II. CONVENTIONAL DELAY BUFFERS
The simplest way to implement a delay buffer is to use shiftregisters as shown in Fig. 1. If the buffer length is and theword-length is , then a total of DFFs are required, and itcan be quite large if a standard cell for DFF is used. In addition,this approach can consume huge amount of power since on theaverage binary signals make transitions in every clockcycle. As a result, this implementation is usually used in shortdelay buffers, where area and power are of less concern.


Download full report
http://ieeexplore.ieeeiel5/92/5208586/04...er=4801521