Abstract
This paper proposes a novel adaptive pseudo-carry compensation truncation (PCT) scheme, which is derived for the multiplexer basedarray multiplier. The proposed method yields low average error among existingtruncation methods. The new PCT based truncated array multiplieroutperforms other existing truncated array multipliers by as much as 25%in terms of silicon area and delay, and consumes about 40% less dynamicpower than the full-width multiplier for 32-bit operation. The proposedtruncation scheme is applied to an image compression algorithm. Due toits low truncation error, the mean square errors (MSE) of various reconstructedimages are found to be comparable to those obtained with full-precisionmultiplication.Index Terms—Computer arithmetic, digital multiplier, truncated multiplier,truncation scheme, VLSI design.
I. INTRODUCTION
Multiplication is a fundamental arithmetic operation used pervasivelyin digital signal processing (DSP) applications like filtering,convolution, and compression [1]. From VLSI perspective, since afull-width digital multiplier receives two single precision operands toproduce a double precision output, it greatly benefits from truncationfor applications with a limited-precision datapath. Due to the noteworthyhardware reduction, the dynamic power dissipation can alsobe proportionally reduced without having to resort to sophisticatedpower reduction techniques.Several truncation schemes have been proposed for fast digital multipliers[2]–[10]. The schemes proposed in [3] and [4] ignore the leastsignificant