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A hybrid approach to nanoelectronics

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G F Cerofolini1,3, G Arena1, C M Camalleri1, C Galati1, S Reina1, L Renna1 and D Mascolo2
1 STMicroelectronics, Stradale Primosole 50, 95100 Catania CT, Italy
2 STMicroelectronics, Via Remo De Feo 1, 80022 Arzano NA, Italy
3 Address for correspondence: STMicroelectronics, 20041 Agrate MI, Italy

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abstraction
. The definition of features on the nanometre length scale (NLS) is impossible via conventional lithography, but can be done using extreme ultraviolet, synchrotron-radiation, or electron beam lithography. However, since these techniques are very expensive and still in their infancy, their exploitation in integrated circuit (IC) processing is still highly putative. Geometries on the NLS can however be produced with relative ease using the spacer patterning technique, i.e. transforming vertical features (like film thickness) in the vicinity of a step of a sacrificial layer into horizontal features. The ultimate length that can be produced in this way is controlled by the steepness of the step defining the sacrificial layer, the uniformity of the deposited or grown films, and the anisotropy of its etching. While useful for the preparation of a few devices with special needs, the above trick does not allow by itself the development of a nanotechnology where each layer useful for defining the circuit should be on the NLS and aligned on the underlying geometries with tolerances on the NLS. Setting up such a nanotechnology is a major problem which will involve the IC industry in the post-Roadmap era. Irrespective of the detailed structure of the basic constituents (molecules, supramolecular structures, clusters, etc), ICs with nanoscopic active elements can hardly be prepared without the ability to produce arrays of conductive strips with pitch on the NLS. This work is devoted to describing a scheme (essentially based on the existing microelectronic technology) for their production without the use of advanced lithography and how it can be arranged to host molecular devices.