A 1-V 36-μW LOW NOISE ADAPTIVE INTERFACE IC FOR PORTABLE BIOMEDICAL APPLICATIONS
SEMINAR REPORT
Submitted by
AKHIL MATHEW
Seventh Semester
B.Tech
Applied Electronics and Instrumentation
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
COLLEGE OF ENGINEERING
TRIVANDRUM
2010
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ABSTRACT
This paper presents an adaptive interface ASIC consisting of a low-noise analog front-end and a successive approximation ADC. The entire analog signal processing chain is fully-differential for better immunity to common-mode noise and interferences. To make the interface adaptive to different biopotential signals, the bandwidth and gain of the analog front-end are configurable. The ADC is designed for rail-to rail operation and the input full-scale is adjustable so that the resolution requirement can be relaxed. Fabricated in 0.18-μm CMOS, 95-nV/√Hz input-referred noise density and more than 100-dB CMRR are obtained. Operating in 10-bit mode, the ADC exhibits -1/+0.3-LSB DNL and -1.3/+0.8-LSB INL for 1-V rail-torail input. The whole interface IC consumes 36 μW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power biomedical applicatons.
TABLE OF CONTENTS
1. INTRODUCTION 6
2. BIOPOTENTIAL AMPLIFIERS 7
2.1 BASIC REQUIREMENTS 7
3. INTERFACE ARCHITECTURE 10
3.1 INSTRUMENTATION AMPLIFIER 12
3.2 ANALOG FRONT END 15
3.3 PROGRAMMABLE GAIN AMPLIFIER
AND DC OFFSET CANCELLATION 17
3.4 SAR ADC 18
4. MEASUREMENT RESULTS 20
4.1 FREQUENCY RESPONSE 22
4.2 NOISE PERFORMANCE 23
4.3 DNL AND INL OF SAR ADC 24
5. CONCLUSION 25
6. REFERENCES 27
CHAPTER 1
INTRODUCTION
Healthcare technologies are increasingly important and have received extensive research interests in recent years. Since the major functions of signal processing are conducted in the digital domain, an analog interface that reproduces the biomedical signal in the digital domain is fundamentally crucial. The quality of signal acquisition and digitization at the interface determines ultimately the performance of the whole system. In addition, a clear trend of healthcare devices is the portability, where low power and low voltage design are desired for longer battery lifetime or even self-powered operations.
Most of biopotential signals are of very low amplitude, e.g. the amplitude of electrocardiography (ECG) signal is around tens of μV to several mV, and the electroencephalography (EEG) signal is at μV level. The bandwidth of the biopotential signals varies from hundred Hz to several kHz. To accommodate different kinds of biomedical signals, the gain and bandwidth of the interface should be adjustable. Meanwhile, the nature of human tissue and the environment result in a lot of noise and interference to the desired signal, e.g. powerline interference, baseline drift and noise due to electrode-skin contact, etc. The analog interface should be able to provide enough dynamic range and noise rejection performance.There are some configurable biomedical front-ends (FE) that have been reported . However, none of them included an analog-to-digital converter (ADC). An ADC-enabled design is reported , but the fixed gain and bandwidth of the front-end prevent any adaptability. In this paper, we present an configurable biomedical interface, where a lowpower successive-approximation ADC is used and the gainand bandwidth of the front-end are digitally adjustable. This enables an adaptive system to different kinds of biomedical applications. The design has been fabricated in a 0.18-μm CMOS technology, and consumes only 36 μW from a single 1- V supply. It is suitable for a wide range of applications where a front-end biopotential interface is required.
CHAPTER 2
BIOPOTENTIAL AMPLIFIERS
Amplifiers are an important part of modern instrumentation systems for measuring biopotentials. Such measurements involve voltages that often are at low levels, have high source impedances, or both. Amplifiers are required to increase signal strength while maintaining high fidelity. Amplifiers that have been designed specifically for this type of processing of biopotentials are known as biopotential amplifiers. In this chapter we examine some of the basic features of biopotential amplifiers and also look at specialized systems.
2.1 BASIC REQUIREMENTS
The essential function of a biopotential amplifier is to take a weak electric
signal of biological origin and increase its amplitude so that it can be further processed, recorded, or displayed. Usually such amplifiers are in the form of voltage amplifiers, because they are capable of increasing the voltage level of a signal. Nonetheless, voltage amplifiers also serve to increase power levels, so they can be considered power amplifiers as well. In some cases, biopotential amplifiers are used to isolate the load from the source. In this situation, the amplifiers provide only current gain, leaving the voltage levels essentially unchanged.
To be useful biologically, all biopotential amplifiers must meet certain
basic requirements. They must have high input impedance, so that they provide minimal loading of the signal being measured. The characteristics of biopotential electrodes can be affected by the electric load they see, which, combined with excessive loading, can result in distortion of the signal. Loading effects are minimized by making the amplifier input impedance as high as possible, thereby reducing this distortion. Modern biopotential amplifiers have input impedances of at least 10 MV.
The input circuit of a biopotential amplifier must also provide protection to the organism being studied. Any current or potential appearing across the amplifier input terminals that is produced by the amplifier is capable of affecting the biological potential being measured. In clinical systems, electric currents from the input terminals of a biopotential amplifier can result in microshocks or macroshocks in the patient being studied—a situation that can have grave consequences. To avoid these problems, the amplifier should have isolation and protection circuitry, so that the current through the electrode circuit can be kept at safe levels and any artifact generated by such current can be minimized.
The output circuit of a biopotential amplifier does not present so many
critical problems as the input circuit. Its principal function is to drive the amplifier load, usually an indicating or recording device, in such a way as to maintain maximal fidelity and range in this readout. Therefore, the output impedance of the amplifier must be low with respect to the load impedance, and the amplifier must be capable of supplying the power required by the load. Biopotential amplifiers must operate in that portion of the frequency spectrum in which the biopotentials that they amplify exist. Because of the low level of such signals, it is important to limit the bandwidth of the amplifier so that it is just great enough to process the signal adequately. In this way, we can obtain optimal signal-to-noise ratios (SNRs).
Biopotential signals usually have amplitudes of the order of a few millivolts or less. Such signals must be amplified to levels compatible with recording and display devices. This means that most biopotential amplifiers must have high gains—of the order of 1000 or greater.Very frequently biopotential signals are obtained from bipolar electrodes. These electrodes are often symmetrically located, electrically, with respect to ground. Under such circumstances, the most appropriate biopotential amplifier is a differential one. Because such bipolar electrodes frequently have a common-mode voltage with respect to ground that is much larger than the signal amplitude, and because the symmetry with respect to ground can be distorted, such biopotential differential amplifiers must have high commonmode- rejection ratios to minimize interference due to the common-mode signal.
A final requirement for biopotential amplifiers that are used both in medical applications and in the laboratory is that they make quick calibration possible. In recording biopotentials, the scientist and clinician need to know not only the waveforms of these signals but also their amplitudes. To provide this information, the gain of the amplifier must be well calibrated. Frequently biopotential amplifiers have a standard signal source that can be momentarily connected to the input, automatically at the start of a measurement or manually at the push of a button, to check the calibration. Biopotential amplifiers that need to have adjustable gains usually have a switch by which different, carefully calibrated fixed gains can be selected, rather than having a continuous control (such as the volume control of an audio amplifier) for adjusting the gain. Thus the gain is always known, and there is no chance of its being accidentally varied by someone bumping the gain control. Biopotential amplifiers have additional requirements that are applicationspecific and that can be ascertained from an examination of each application. To illustrate some of these, let us first consider the electrocardiogram (ECG),the most frequently used application of biopotential amplifiers.
CHAPTER 3
INTERFACE ARCHITECTURE
The architecture of the interface IC consists basically of three functional blocks: a front-end instrumentation amplifier (IA), an analog signal conditioning block including a band-pass filter (BPF) and a programmable gain amplifier (PGA), and a successive-approximation register (SAR) type ADC. Since a lot of noise and interference to the biomedical signal are of common-mode characteristics, the fully-differential architecture is exploited for better immunity to the common-mode noise. Note that the input signal is DC-coupled directly from the
electrodes, which avoids large AC-coupling capacitors that have to be placed off-chip. On the other hand, the DC-coupling of signal brings extra offset introduced by electrodes, which has to be accommodated by the input stage of the IA. The bandwidth and gain of the analog signal conditioning blocks are digitally controllable, so that the adaptive control logic can be easily integrated in the digital domain. For ADC, a resolution of 10–12 bits is usually proposed when it is used after the analog signal conditioning. In this design, however, the resolution requirement is relaxed by adapting the input full-scale of the ADC. Since the input of the ADC is differential, it is then possible to control the input range of ADC conversion, e.g., if the input signal of ADC is around 0.3–0.7 V, then the input full-scale of the ADC can be adjusted to 0.2–0.8 V. In other words, the ADC is adaptable and the resolution requirement can be relaxed, which permits lower power consumption. Here a 10-bit ADC is employed. Note that the adjustment of ADC full-scale is limited by the kT/C noise and other considerations. Since the supply voltage is only a single 1 V, the maximum full-scale voltage is designed ±1 V (differential) rail-to-rail.
3.1 INSTRUMENTATION AMPLIFIER
An instrumentation (or instrumentational) amplifier is a type of differential amplifier that has been outfitted with input buffers, which eliminate the need for input impedance matching and thus make the amplifier particularly suitable for use in measurement and test equipment. Additional characteristics include very low DC offset, low drift, low noise, very high open loop gain, very high common mode rejection ratio, and very high input impedances. Instrumentation amplifiers are used where great accuracy and stability of the circuit both short- and long-term are required.
Although the instrumentation amplifier is usually shown schematically identical to a standard op-amp, the electronic instrumentation amp is almost always internally composed of 3 op-amps. These are arranged so that there is one op-amp to buffer each input (+,−), and one to produce the desired output with adequate impedance matching for the function.
The most commonly used instrumentation amplifier circuit is shown in the figure. The gain of the circuit is
The rightmost amplifier, along with the resistors labelled R2 and R3 is just the standard differential amplifier circuit, with gain = R3 / R2 and differential input resistance = 2•R2. The two amplifiers on the left are the buffers. With Rgain removed (open circuited), they are simple unity gain buffers; the circuit will work in that state, with gain simply equal to R3 / R2 and high input impedance because of the buffers. The buffer gain could be increased by putting resistors between the buffer inverting inputs and ground to shunt away some of the negative feedback; however, the single resistor Rgain between the two inverting inputs is a much more elegant method: it increases the differential-mode gain of the buffer pair while leaving the common-mode gain equal to 1. This increases the common-mode rejection ratio (CMRR) of the circuit and also enables the buffers to handle much larger common-mode signals without clipping than would be the case if they were separate and had the same gain.
Another benefit of the method is that it boosts the gain using a single resistor rather than a pair, thus avoiding a resistor-matching problem (although the two R1s need to be matched), and very conveniently allowing the gain of the circuit to be changed by changing the value of a single resistor. A set of switch-selectable resistors or even a potentiometer can be used for Rgain, providing easy changes to the gain of the circuit, without the complexity of having to switch matched pairs of resistors.
3.2 ANALOG FRONT-END
The consideration of the IA design is mainly on the noise performance. As the first stage that interfaces with electrodes directly, the noise performance of the IA determines fundamentally the overall noise performance. The CMRR of IA is also crucial. As mentioned previously, the IA has to accommodate DC-coupled input that can drift up to ±200 mV. Here a folded-cascode opamp with PMOS input pairs is employed as the first stage of the IA. Since the biomedical signals are within the 1/f noise region, chopper technique is exploited at the first stage. Note that the gain of the IA could not be very high, otherwise the interference may saturate the circuits. Meanwhile, a low-gain first stage is not favored considering the noise contributed in the following stages. In this design, the gain of IA is set to a fixed value of 20 V/V. The two functions, BPF and PGA, are implemented using the same configuration . For each amplifier, the gain is determined by C1/C2, and the high-cutoff frequency is determined by the load. This configuration is used here because it is of very good noise performance. The gain is controlled by switching the capacitors in parallel with C1; and the bandwidth is controlled by switching the load capacitors. This architecture permits higher flexibility in controlling the gain and bandwidth, or concurrently. Note that although the two control stages are similar, the BPF function should always be prior to PGA function so as to prevent out-of-band interference from saturating these stages. Since the gain can only be increased and the bandwidth can only be decreased, the basic circuits without the controlling capacitors set the lowest gain and highest bandwidth, which are 2 V/V and 5 kHz respectively.
ANALOG SIGNAL CONDITIONING CIRCUITS (BPF and PGA) WITH CONFIGURABLE BANDWIDTH AND GAIN.
3.3 PROGRAMMABLE GAIN AMPLIFIER AND DC OFFSET CANCELLATION
In a DC offset cancellation circuit, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor connected between the inverse terminal and the output terminal. A DC offset cancellation resistor is connected between the inverse terminal and the non-inverse terminal. Also, in each of first and second DC offset cancellation circuits of the programmable gain amplifier, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor is connected between the inverse terminal and the output terminal. A DC offset cancellation circuit is connected between the inverse terminal and the non-inverse terminal. Here, the first and second DC offset cancellation circuits are connected with each other in series.
3.4 SAR ADC
The SAR ADC is suitable for low-voltage low-power applications with relatively low sampling rate. A charge redistribution DAC based SAR ADC is used in this design. The reference voltages, VREFP and VREFN, set the full-scale voltage of the ADC as ±(VREFP –VREFN). Therefore, the ADC full-scale can be controlled by switching to several preset reference voltages. With the adaptive control of the ADC full-scale voltage, the resolution requirement can be relaxed, which permits lower power for the ADC. Note that with the reduction of the full-scale voltage, the LSB value is also reduced. The minimum LSB should be sufficiently larger than the kT/C noise and other noise sources. In this design, a fully-differential array of capacitors is employed in the DAC; and the unit capacitor size is chosen so that the minimum full-scale voltage is ±0.5 V.
The maximum full-scale voltage of the ADC is ±1 V rail-to-rail. A major factor that limits the resolution of SAR ADC is the matching of large capacitor array; here the common-centroid layout is employed for capacitor matching. Meanwhile, unlike the comparator of pipeline ADC, the comparator used in SAR ADC has to provide full resolution. Considering the full-scale of the ADC is rail-to-rail and there are extra low-frequency noise and offset exist, the comparator is the most power consuming block in the SAR ADC design. Here a multistage comparator with both input and output offset-cancellation is employed . Note that for the preamplifier of the comparator, a complementary input stage with both PMOS and NMOS input pairs is used. Simulation shows that the comparator is able to provide 14-bit resolution with offset up to 100 mV.
BLOCK DIAGRAM OF THE FULLY DIFFERENTIAL SAR ADC.
CHAPTER 4
MEASUREMENT RESULTS
The interface IC was fabricated in a 0.18-μm CMOS technology. The microphotograph of the chip shows the core area of the interface is 3.2mm×2.8mm, and most of silicon area is consumed by capacitors. The analog front-end including IA, BPF and PGA consumes 21 μW from a single 1-V supply. The measured frequency response of the analog front-end gives myriad results. It is measured that the gain is configurable from 31 dB to 52 dB. The bandwidth is configurable from 500 Hz to 4.3 kHz, which covers the spectrum of most biomedical signals. The measured noise performance , where the 50-Hz and 150-Hz spurs are due to the interference from power-line and environment. The input-referred noise (IRN) density is 95 nV/√Hz at 100 Hz, the integrated noise from 0.1 Hz to 200 Hz is 1.9 μVrms. The ADC operates up to 18 kS/s and consumes 15 μW from 1-V supply. The INL and DNL of the ADC are measured The DNL is within -1/+0.3 LSB and the INL is within -1.3/+0.8 LSB. As mentioned previously, the resolution requirement of the ADC is relaxed with the adaptive control of the full-scale voltage. At 2 kS/s, the output spectrum from a 827-Hz analog input can be measured. The SFDR is 64 dB and SNDR is 54 dB, resulting in the ENOB of 8.7 bit. Finally, the interface IC has been employed in a real ECG measurement scenario with Ag/AgCl electrodes. Fig. 10 shows the extracted ECG signals. It is shown that the noise and interference have been suppressed to a relatively low level as compared to the ECG waveform.
The performance achieved in this design is compared with
other state-of-the-art designs for biomedical applications. As
shown in TABLE I, this is the first adaptive biomedical
interface consisting of both front-end and ADC
CHAPTER 5
CONCLUSION
An adaptive interface IC has been demonstrated including a low-noise signal acquisition front-end and a SAR ADC. For better immunity to the common-mode noise and interference, the design employed fully-differential architecture in the entire analog signal processing path. Both the front-end and the ADC are digitally controllable, leading to an adaptive interface capable of a wide range of biomedical applications. The inputreferred noise density was 95 nV/√Hz and more than 100 Db CMRR was achieved. The resolution requirement of the ADC has been relaxed with the adaptive full-scale range. The ADC exhibited less than ±1-LSB DNL and ±1.3-LSB INL. The whole interface consumed only 36 μW from a low supply voltage of 1 V, making it suitable for voltage and power constrained applications.
CHAPTER 6
REFERENCES
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Papers, San Francisco, CA, Feb. 5–9, 2006, pp. 56–57.
[2] K. A. Ng and P. K. Chan, “A CMOS analog front-end IC for portable EEG/ECG monitoring applications,” IEEE Trans. Circuits Syst.—I: Regular
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[3] R. F. Yazicioglu, P. Merken, R. Puers, and C. V. Hoof, “Low-power low-noise 8-channel EEG front-end ASIC for ambulatory acquisition systems,” in 2006 European Solid-State Circuits Conf. (ESSCIRC), Montreux,
Switzerland, Sep. 18–22, 2006, pp. 247–250.
[4] M. Shojaei-Baghini, R. K. Lal, and D. K. Sharma, “A low-power and compact analog CMOS processing chip for portable ecg recorders,” in 2005 IEEE Asian Solid-State Circuits Conf. (ASSCC), Hsinchu, Taiwan,
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