presented by;
Abhishek A. B

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Abstract—This paper surveys recent publications on the new class of layered circuit integration techniques termed 3D integration. We describe both the potential benefits and major pitfalls of 3D integration. Several competing layering approaches are described and compared. We also forecast the impact that a move to 3D integration would have on CAD tools and circuit design flows. Sequential fabrication of CMOS devices one above the other on isolated crystalline templates could enable the manufacture of 3D Integrated circuits with more than a million inter-layer wires per square millimeter. 3D IC technologies can help to improve circuit performance and lower power consumption by reducing wire length. Also, 3D IC technology can be used to realize heterogeneous system-on-chip design, by integrating different modules together with less interference with each other. Through strategic modification of the architectures to take advantage of 3D, significant improvement in speed and reduction in power consumption can be achieved.
Introduction- One of the main factors that limit the performance of today’s integrated circuits (ICs) is their architecture. In today’s integrated circuits the building blocks or the transistors are laid out like singlestoried buildings spread out over large areas on the top surface of the silicon wafer. Imagine how compact these circuits could be made, if the transistors were stacked one above the other – to resemble the tall skyscrapers in downtown Manhattan. Bringing the components closer to each other in this manner could not only make these systems faster owing to a reduction in the average length of the interconnect wires, but also more versatile because more and more transistors could be crammed in a relatively small area . The ‘3D-ness’ of an IC can be assessed by comparing the density of vertical interconnect wires running between the different device levels to the number of wires (vias) per unit area of a conventional IC. 3D-IC promises to offer multiple advantages over conventional 2D-IC, including alleviating the communication bottleneck, integration of heterogeneous materials, and enabling novel architectures. 3D-ICs present challenges at all fronts of technology and design. If the 3D-IC is simply a stacking of the 2D circuit blocks with no significant modification in architecture, the gain in performance will be very limited, if any. A strategy in architecture and function partitioning across layers must be developed to take advantage of the third dimension while managing the overall complexity. The performance advantages of 3D architectures will be illustrated with two examples: 3D-FPGA and 3D-SRAM.
The first and most obvious, potential motivation is miniaturization. However, through silicon 3D integration is rarely justified by the desire for miniaturization alone. For most circumstances, if volume reduction is the only goal, then it is much more cost effective to stack and wire-bond. This technology is already in wide-spread use in cell phones, and continues. However, one exception that is being widely explored is for memories. Wire-bonding cannot be easily used to stack identical memory chips, as they are all the same size. In addition, there are systems advantages to thinning and stacking multiple memory die such that the aggregate memory has the same end form factor as one memory package. For example, this technology could enable a credit card sized video storage and viewing device containing 100s of hours of video.
3D IC technologies can help to improve circuit performance and lower power consumption by reducing wire length. Also, 3D IC technology can be used to realize heterogeneous system-on-chip design, by integrating different modules together with less interference with each other.
In this section we motivate (A) higher levels of integration, (B) the shortening of interconnect, © heterogeneous integration, and (D) fine grained testing. 3D integration facilitates each of these tasks.
A. Systems on Chip
The System on Chip (SoC) has become an attractive option due to technology scaling. A SoC is a complete electronic system, including digital logic, memory, and analog circuitry, in a single chip. The reasons for this development are clear. In the fabrication of integrated circuits, yield drops off dramatically with increased die area. For this reason, die areas have only slowly increased over the years. Transistor density, on the other hand, has maintained an exponential growth trajectory for decades. As VLSI transistor sizes decrease, more functionality can be integrated onto a given die area. At the same time, pads and PCB traces outside of a chip become larger relative to those smaller transistors within chip; both the power and latency of off-chip communication increase relative to on-chip communication. In addition to growth in the number of pins available on chip packages is relatively slow; this limits off-chip communication bandwidth. Therefore, there is both the capability and motivation to integrate more system components onto a single die.
B. Interconnect shortening
With increasing per-die circuit size, both in SoCs and in complex monolithic instruction processors, interconnect delay has become the dominant factor for circuit performance. Larger circuit sizes mean global wires connecting opposite ends of the die are larger relative to transistors; their delay now dominates gate delay. The dominance of interconnect delay has also created a timing closure problem for CAD tools. Physical layout and routing decisions must be fed back into the tools that synthesize logic and size gates in order to verify that timing deadlines are indeed met; as interconnect delay becomes more dominant, it becomes more difficult to predict path delays in the early stages and thus the chances of meeting deadlines after physical design are lowered. Infinite iteration between high and low level designs can result. Repeater insertion is another headache for hierarchical design flows. Delay along global wires can be reduced by breaking them up with repeaters. However, these repeaters must be squeezed into valuable silicon area underneath the wire. Routing is usually done after placement, so we have a feedback situation akin to timing closure: It would be highly advantageous to reduce the delay penalties and design complexities due to long interconnects. We can see that 3D integration does this by simple geometry. A given square area A has maximum Manhattan wire length 2√A. The same area split into two layers reduces the wire length to √2√A+lv where lv is the length of a via between layers. In general, n layers give a maximum Manhattan wire length of
2√ (A/n) + (n - 1)lv.
C. Heterogeneous integration
In a mixed design, like a SoC, we prefer to fabricate each type of circuit in its own ideal technology; a 3D system allows layers built with different processes to be combined into a single chip. It is possible to fabricate digital logic, memories, DSPs, analog and RF devices on a single die using one technology but this is suboptimal in terms of performance, area, and power. Putting the components on different dies also allows us to better isolate sensitive analog circuitry. Even within the same process, it may be desirable to have layers with different voltage and performance requirements or clocking domains. Looking ahead, heterogeneous layering also would allow the upper layer to be dedicated to optical I/O and low-skew optical clock distribution.