I need code for 16bit vedic multiplier using urdhva thiryagbhyam.

16 bit multiplier verilog code

module q_1_2 (input [15:0]x,y, output [31:0]z);

parameter size=256, width=16;
wire [size-1:0]pi,ci,po,co;

genvar i,j;
generate

for (j=0;j<16;j=j+1) assign pi[width*0+j]=0;
for (i=0;i<16;i=i+1) assign ci[width*i+0]=0;
q_1_1 eb0_0 (x[0],y[0],pi[o],ci[0],po[0],co[0]);

for (j=1;j<16;j=j+1) begin
assign ci[width*0+j] = co[width*0+(j-1)];
q_1_1 eb0_j (x[0],y[j],pi[width*0+j],ci[width*0+j],po[width*0+j],co[width*0+j]);
end

for (i=1;i<16;i=i+1) begin
assign pi[width*i+0] = po[width*(i-1)+0];
q_1_1 ebi_0 (x[i],y[0],pi[width*i+0],ci[width*i+0],po[width*i+0],co[width*i+0]);
end

for (i=1;i<16;i=i+1) begin
for (j=1;j<15;j=j+1) begin
assign ci[width*i+j] = co[width*i+(j-1)];
assign pi[width*i+j] = po[width*(i-1)+j];
q_1_1 ebi_j (x[i],y[j],pi[width*i+j],ci[width*i+j],po[width*i+j],co[width*i+j]);
end

assign ci[width*i+15] = co[width*i+14];
assign pi[width*i+15] = co[width*(i-1)+15];
q_1_1 ebi_15 (x[i],y[15],pi[width*i+15],ci[width*i+15],po[width*i+15],co[width*i+15]);
end

for (i=0;i<16;i=i+1) assign z[i] = po[width*i+0];
for (j=1;j<16;j=j+1) assign z[j+15] = po[width*15+j];
assign z[31] = co[width*15+15];

endgenerate
endmodule