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Title: CMOS TIME INTERLEAVED ADC
Page Link: CMOS TIME INTERLEAVED ADC -
Posted By: shibin.sree
Created at: Monday 28th of December 2009 09:31:23 PM
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ABSTRACT

A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b backend folding ADC. The full-scale residue range at the output of the pipeline ....etc

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Title: some project topics related to commerce
Page Link: some project topics related to commerce -
Posted By:
Created at: Monday 28th of January 2013 04:02:03 PM
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Title: seminar on interfacing of adc with arm processor
Page Link: seminar on interfacing of adc with arm processor -
Posted By:
Created at: Monday 01st of October 2012 09:38:31 PM
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Title: CMOS TIME INTERLEAVED ADC full report
Page Link: CMOS TIME INTERLEAVED ADC full report -
Posted By: seminar presentation
Created at: Friday 21st of May 2010 10:18:40 PM
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ABSTRACT
A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b “backend” folding ADC. The full-scale re ....etc

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Title: some oral presentation topics for communication lab
Page Link: some oral presentation topics for communication lab -
Posted By:
Created at: Tuesday 15th of July 2014 10:11:28 PM
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Title: pc as cro and signal storage using cpp and adc
Page Link: pc as cro and signal storage using cpp and adc -
Posted By: upendra256
Created at: Sunday 08th of August 2010 08:52:21 PM
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Title: sir i urgently need some latest ieee seminars topics as fast as possibleplease
Page Link: sir i urgently need some latest ieee seminars topics as fast as possibleplease -
Posted By: jinunjacob
Created at: Saturday 01st of October 2011 02:59:46 PM
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Title: please let me know some of the latest seminars topics
Page Link: please let me know some of the latest seminars topics -
Posted By: athulya
Created at: Thursday 26th of August 2010 05:51:44 PM
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Title: MONOLITHIC LOW-POWER 16 B 1 SAMPLES SELF-CALIBRATING PIPELINE ADC
Page Link: MONOLITHIC LOW-POWER 16 B 1 SAMPLES SELF-CALIBRATING PIPELINE ADC -
Posted By: computer science crazy
Created at: Friday 18th of September 2009 12:27:50 AM
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MONOLITHIC LOW-POWER 16 B 1 SAMPLE/S SELF-CALIBRATING PIPELINE ADC

Abstract:- Pipelined architectures enable the implementation of high-speed, high-resolution, low-power analog-to-digital converters (ADCs). Concurrent processing of analog signals results in power and/or speed advantages over flash and multi step ADC architectures. While self-calibration techniques reduce the effects of component mismatches, the digital crosstalk due to correction circuitry can degrade the noise and linearity performance of the overall converter. Previous pip ....etc

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Title: need help in some of this topics
Page Link: need help in some of this topics -
Posted By: movingcoil
Created at: Tuesday 05th of April 2011 06:35:52 PM
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am a student of electrical engineering but wants to major in telecommunications.
Need some help in these seminar topics that am writing on and some guidelines..
Please if anyone has anything to help me with please should send it to my inbox [email protected].
will be very grateful
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