hello........
i am Rupa devi pursuing b-tech final year (IT branch) from a JNTU affliated college and i would request you to post or mail the document related to the project title as mentioned.
and my problem regarding this project is that i am not able to understand the algorithm present in it and how i need to implement it.I know java programming language and i am doing my project haf way through .
so please post the related information about it .

Abstract :This paper presents the IMine index, a general and compact structure which provi ....etc

[:=Read Full Message Here=:]

ABSTRACT


A protocol designed to ensure the security and integrity of online communications and purchases, Secure Electronic Transaction (SET) uses digital certificates, issued to merchants and other businesses and customers, to perform a series of security checks verifying that the identity of a customer or sender of information is valid. SET provides the basic framework within which many of the various components of securing digital transactions function. Digital certificates, digital signatures, and digital ....etc

[:=Read Full Message Here=:]

presented by:Tushar Karayil Ravindran
Randomized Instruction Set Emulation

Abstract
This topic deals with the security issue facing the modern computer systems.All the systems follow a specific standard to make them compatible and independent.So it is easy for an attacker to hit the vulnerability since he knows the standard that the system follows .Moerover the same attack will be successfull on al ....etc

[:=Read Full Message Here=:]

Assessment of SET Logic Robustness Through Noise Margin Modeling

Chaitanya Sathe, Surya Shankar Dan, and Santanu Mahapatra, Member, IEEE

Abstract—
A compact model for noise margin (NM) of single electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (ζ). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (CG and CT ....etc

[:=Read Full Message Here=:]

Jini provides facilities for dealing with some of the Fallacies of Distributed Computing, problems of system evolution, resiliency, security and the dynamic assembly of service components. Code mobility is a core concept of the platform and provides many benefits including non-Protocol dependence. The Jini team at Sun Microsystems has always stated that Jini is not an acronym. Some have joked that it meant Jini Is Not Initials, but it's always been just Jini. The word Jini means the devil in Kiswahili; this is a loan from an Arabic word for ....etc

[:=Read Full Message Here=:]

Introduction

Many decision-making and problem-solving tasks are too complex to be understood quantitatively, however, people succeed by using knowledge that is imprecise rather than precise. Fuzzy set theory, originally introduced by Lotfi Zadeh in the 1960's, resembles human reasoning in its use of approximate information and uncertainty to generate decisions. It was specifically designed to mathematically represent uncertainty and vagueness and provide formalized tools for dealing with the imprecision intr ....etc

[:=Read Full Message Here=:]

Discriminative Learing and Recognition of Image set classes Using Canonical Correlation

Abstract:

Canonical angles or principle angle between the two dimensional sub-space.

Canonical angle is compared with the two main classical methods: parametric distribution based and non parametric sample based.

The classical linear discriminate analysis which we have to develop is to be maximizing the correlation with-in the class set and it has to minimize between the class-set.

Image set after transforming the discrimi ....etc

[:=Read Full Message Here=:]

Single electron tunneling (SET) transistor

ABSTRACT
The chief problem that are faced by chip designers are regarding the size of the chip. According to Moores„¢s Law, the number of transistors on a chip will approximately double every 18 to 24 months. Moore\'s Law works largely through shrinking transistors-the circuits that carry electrical signals. By shrinking transistors, designers can squeeze more transistors into a chip. However, more transistors means more electricity and heat compressed into an even smaller space. F ....etc

[:=Read Full Message Here=:]

Reduced Instruction Set Computer (RISC) processor

INTRODUCTION
This project is aimed at designing of a Reduced Instruction Set Computer (RISC) processor using the Verilog Hardware Description Language (HDL). For a long time, programming languages such as C, Pascal & FORTRAN were being used to describe the computer programs that were sequential in nature. Similarly in the digital design field, designers felt the need for a standard language to describe digital circuits. Thus, HDL came into exi ....etc

[:=Read Full Message Here=:]

Difference between CISC and RISC:
CISC stands for Complex Instruction Set Computer. Most PC's use CPU based on this architecture. For instance Intel and AMD CPU's are based on CISC architectures. Typically CISC chips have a large amount of different and complex instructions. In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions. MCS-51 family microcontrollers based on CISC architecture.
RICS stands for Reduced Instruction Set Computer ....etc

[:=Read Full Message Here=:]