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Title: comparative study between eddy current loss in laminated core and embedded core
Page Link: comparative study between eddy current loss in laminated core and embedded core -
Posted By: seminar project explorer
Created at: Sunday 13th of March 2011 04:51:30 PM
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Transformer Basics
An electrical device that transfers energy from one circuit to another purely by magnetic inductive coupling.

Review of transformer losses
No load Loss (Excitation Loss) includes the hysteresis loss and eddy current loss.
excitation loss: energy lost by reversing the magnetic field in the core by the alternating AC.
mechanical loss: bearing friction,brush friction and windage loss

Load Loss (Impedance Loss)
Stray loss: It includes distortion of air-gap flux and also due to the due to non uniform ....etc

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Title: Future evolution of microprocessor from single core to multi core
Page Link: Future evolution of microprocessor from single core to multi core -
Posted By: [email protected]
Created at: Monday 07th of February 2011 03:20:16 PM
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Dusa Sindhoori
B.Tech
Sree Chaitanya College Of Engineering
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Karimnagar

I want the abstract,ppt,documentation and details about the topic Future evolution of microprocessor from single core to multi core
please send these details to [email protected]
please send the details which i requested ....etc

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Title: Differentiated Bandwidth Allocation with TCP Protection in Core Routers
Page Link: Differentiated Bandwidth Allocation with TCP Protection in Core Routers -
Posted By: computer science crazy
Created at: Thursday 17th of September 2009 05:27:00 AM
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Differentiated Bandwidth Allocation with TCP Protection in Core Routers


Abstract

Differentiated Services (DiffServ) networks categorize routers into edge routers and core routers.In core routers, one of the technological challenges is how to implement differentiated bandwidth allocation and TCP protection together with low complexity.We present an Active Queue Management (AQM) scheme called CHOKeW. A method is borrowed from a previous scheme, CHOKe, which draws a packet at random from the buffer, compares it with the arriving packet, a ....etc

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Title: Hyperthreading
Page Link: Hyperthreading -
Posted By: iitbuji
Created at: Saturday 24th of October 2009 04:35:34 PM
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Hyper-Threading Technology brings concept of simultaneous multi-threading to the Intel Architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors. The physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. From a ....etc

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Title: Open Wireless Architecture - The Core to 4G Mobile Communications
Page Link: Open Wireless Architecture - The Core to 4G Mobile Communications -
Posted By: computer science crazy
Created at: Sunday 20th of September 2009 06:49:40 PM
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Open Wireless Architecture - The Core to 4G Mobile
Communications


Abstract


Mobile communication is continuously one of the
hottest areas that are developing at a booming speed,
with advanced techniques emerging in all the fields of
mobile and wireless communications. Current times
are just the beginning for deploying 3G mobile
communication systems, while research on the next
generation of mobile communications, 4G wireless and
mobile networks begin to pave the way for the future.
This article studies the visions of 4G from ....etc

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Title: debug probe debugging multiple embedded cores and inter-core transactions in NoC
Page Link: debug probe debugging multiple embedded cores and inter-core transactions in NoC -
Posted By: computer science crazy
Created at: Wednesday 21st of October 2009 11:14:57 PM
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ABSTRACT

Existing SoC debug techniques mainly target bus-based systems. They are not readily applicable to the emerging system that use Network-on-Chip (NoC) as on-chip communication scheme. In this paper, we present the detailed design of a novel debug probe (DP) inserted between the core under debug (CUD) and the NoC. With embedded configurable triggers, delay control and time stamping mechanism, the proposed DP is very effective for inter-core transaction analysis as well as controlling embedded cores' debug processes. Experimental result ....etc

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Title: Hyperthreading Download The Seminar Report
Page Link: Hyperthreading Download The Seminar Report -
Posted By: computer science crazy
Created at: Tuesday 07th of April 2009 11:08:45 PM
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Hyper-Threading (HT) Technology is a groundbreaking innovation from Intel that improves PC responsiveness, produces performance gains of up to 25 percent.
Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. ....etc

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Title: Dual Core Processor
Page Link: Dual Core Processor -
Posted By: computer science crazy
Created at: Tuesday 23rd of September 2008 03:51:38 AM
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Definition

Seeing the technical difficulties in cranking higher clock speed out of the present single core processors, dual core architecture has started to establish itself as the answer to the development of future processors. With the release of AMD dual core opteron and Intel Pentium Extreme edition 840, the month of April 2005 officially marks the beginning of dual core endeavors for both companies.

The transition from a single core to dual core architecture was triggered by a couple of factors. According to Moore's Law, the number o ....etc

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Title: Dual-Core Processors
Page Link: Dual-Core Processors -
Posted By: seminar projects crazy
Created at: Wednesday 28th of January 2009 04:08:14 PM
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Computer performance has been driven largely by decreasing the size of the chips while increasing the number of transistors they contain. In accordance with Moore?s law, this has caused chip speed to rise and prices to drop. However transistors can?t shrink forever. As components grow thinner, chip manufactures have struggled to cap power usage and heat generation. Even performances enhancing approaching like running multiple instructions per thread have bottomed out. In response manufactures are building chips with multiple cooler running, mor ....etc

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Title: dual core processors
Page Link: dual core processors -
Posted By: shibin.sree
Created at: Friday 18th of December 2009 05:53:33 PM
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If you have you lost count of the times you find your computer lagging when you work on several AutoCAD projects while also zipping your entire C drive, and burning a series of CDs, or if youâ„¢ve just hoped that you could find an expensive new computer feature that is more status symbol than performance, here the answer; you should be happy to hear about the new systems work.A dual-core processor is a CPU with two separate cores on the same die, each with its own cache. Itâ„¢s the equivalent of getting ....etc

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