VLSI Design and Implementation of Low Power MAC Unit with
Block Enabling Technique

Abstract
In the majority of digital signal processing (DSP) applications the critical operations
are the multiplication and accumulation. Real-time signal processing requires high speed
and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which
is always a key to achieve a high performance digital signal processing system. The
purpose of this work is, design and implementation of a low power MAC uni ....etc

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Design and implementation of multi-channel CAN Communication Interface based on Embedded Linux
Abstract –
According to the communication and controlrequirement of multi-channel Control Area Network(CAN)bus by the HLA simulation platform, this paper described aembedded PowerPC system based method of design andimplementation of multi-channel CAN communicationplatform. The corresponding Linux multi-channel CAN devicedriver has also been developed. This flexible system canconnect to different number of CAN daughter boards. It canwork st ....etc

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Implementation of RSA Algorithm Using Client-Server
Presented By:
GAUTHAM R

Introduction
In cryptography, RSA (which stands for Rivest, Shamir and Adleman ) is an algorithm for public-key cryptography.
It is the first algorithm known to be suitable for signing as well as encryption.
RSA is widely used in electronic commerce protocols, and is believed to be secure given sufficiently long keys and the use of up-to-date implementations.
Network security threats
Network Security Threats
Cryptography
Security in net ....etc

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Abstract
In the majority of digital signal processing (DSP) applications the critical operations
are the multiplication and accumulation. Real-time signal processing requires high speed
and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which
is always a key to achieve a high performance digital signal processing system. The
purpose of this work is, design and implementation of a low power MAC unit with block
enabling technique to save power. Firstly, a 1-bit MAC unit is designed, with appropriate
geom ....etc

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requirement
Required full documentation of design of a random testing circuit based on lfsr for external memory interface.
I didn't get any required information. can you please send me the full documentation of DESIGN OF A RANDOM TESTING CIRCUIT BASED ON LFSR FOR THE EXTERNAL MEMORY INTERFACE ....etc

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Design and Implementation of Multiple Cryptographic Algorithm Interface Circuit Based on Secure SoC
Abstract-
Based on the requirements of integrating multiple
cryptographic algorithm IP cores into secure SoC, after
analyzing the existing design of interface circuit, an interface
circuit of the multiple cryptographic algorithm IP core is
designed and implemented in this paper. Using the bridge
technology, it achieves the dynamic reconfiguration of three
cryptographic algorithm IP cores-AES, ECC and SHAI tied to
one dual-port RA ....etc

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This article describes a DDR SDRAM (Double Data Rate Synchronously
Dynamic RAM) controller. The commands of the FPGA-based DDR
SDRAM controller is described in detail. The Verilog HDL is used to implement the R/W operation of the DDR SDRAM. This controler isused to control a 400MHz single channel high-speed, high-precision and large-capacity data acquisition board.

Introduction
The speed and precision of data acquisition system must be sufficiently high to meet the requirements of advanced communication technology development. h ....etc

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Abstract

This thesis is intended to explore the major technical challenges facing developers and authors of online help systems who need to integrate online help features into proprietary software programs in a local or network setting, which involves adoption of proven strategies of help system design and help documentation analysis. It discusses the help system development process using the architecture of reusable JavaHelp components from Sun Microsystems. It also explains the programming details of building a sample help system as ....etc

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iam a b.tech student currently wrkng on a prjct on cs protocol implementation. iam here to gather info about latest prjcts. ....etc

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ABSTRACT
DDR2 SDRAM or double-data-rate two synchronous dynamic random access memory is a computer memory technology. It is a refinement to the existing DRAM technology. JEDEC (Joint Electron Device Engineering Council) which provides standards for memory technologies has standardized this technology.
Double Data Rate and Dual channel Architecture enhances memory performance. DDR2 requires less space and provides high density modules .Power consumption is also less which makes DDR2 a favorite user choice.
DDR2 increases ....etc

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