31-05-2017, 05:13 PM
01-06-2017, 09:22 AM
VHDL is the industry standard language for the modeling, description and synthesis of circuits and digital systems. It extends as very high-speed integrated circuits (VHISC). It needs a standard language to describe the structure and function of integrated circuits (IC).
VHDL is suitable with programmable logic devices for design. Now engineers can achieve a fast and efficient design with the help of large capacity CPLDs and FPGAs from 500 to 100,000 gates. This language is a high level language to describe the big circuits to the market quickly.
VHDL supports the creation of libraries to store components for reuse in particular designs. It provides the code probability between the synthesis and simulation tools. It is a device of independent design. It also converts a design from a programmable logic to an ASIC implementation.
VHDL allows log-log transfer and logic gate level. With the help of VHDL, a user is able to abstract the implementation details of a design. VHDL provides mixed-level design described at a high level of abstraction and also at a lower level of abstraction. The mixed level simulation focuses on the design of critical timing modules.
VHDL describes a model for a digital hardware device. Specifies the external and internal views of the device. The building blocks of the VHDL language are Entity, Architecture, Package and Process. There are different styles of modeling, such as data flow modeling style, structural modeling style and modeling behavior style, etc.