04-06-2012, 05:21 PM
Complementary MOS fabrication
[attachment=54]
CMOS Technology depends on using both N-Type and P-Type devices on the same chip.
The two main technologies to do this task are:
P-Well (Will discuss the process steps involved with this technology)
The substrate is N-Type. The N-Channel device is built into a P-Type well within the parent N-Type substrate. The P-channel device is built directly on the substrate.
N-Well
The substrate is P-Type. The N-channel device is built directly on the substrate, while the P-channel device is built into a N-type well within the parent P-Type substrate.
Two more advanced technologies to do this task are:
Becoming more popular for sub-micron geometries where device performance and density must be pushed beyond the limits of the conventional p & n-well CMOS processes.
Twin Tub
Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate.
Silicon-on-Insulator (SOI) CMOS Process
SOI allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.
P-well on N-substrate
Steps :
N-type substrate
Oxidation, and mask (MASK 1) to create P-well (4-5m deep)
P-well doping
P-well acts as substrate for nMOS devices.
The two areas are electrically isolated using thick field oxide (and often
isolation implants [not shown here])
Twin-Tub (Twin-Well) CMOS Process
This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently. Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics. The Twin-Tub process is shown below.
Silicon-on-Insulator (SOI) CMOS Process
Rather than using silicon as the substrate material, technologists have sought to use an insulating substrate to improve process characteristics such as speed and latch-up susceptibility. The SOI CMOS technology allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate. The main advantages of this technology are the higher integration density (because of the absence of well regions), complete avoidance of the latch-up problem, and lower parasitic capacitances compared to the conventional p & n-well or twin-tub CMOS processes. A cross-section of nMOS and pMOS devices using SOI process is shown below.
[attachment=54]
CMOS Technology depends on using both N-Type and P-Type devices on the same chip.
The two main technologies to do this task are:
P-Well (Will discuss the process steps involved with this technology)
The substrate is N-Type. The N-Channel device is built into a P-Type well within the parent N-Type substrate. The P-channel device is built directly on the substrate.
N-Well
The substrate is P-Type. The N-channel device is built directly on the substrate, while the P-channel device is built into a N-type well within the parent P-Type substrate.
Two more advanced technologies to do this task are:
Becoming more popular for sub-micron geometries where device performance and density must be pushed beyond the limits of the conventional p & n-well CMOS processes.
Twin Tub
Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate.
Silicon-on-Insulator (SOI) CMOS Process
SOI allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.
P-well on N-substrate
Steps :
N-type substrate
Oxidation, and mask (MASK 1) to create P-well (4-5m deep)
P-well doping
P-well acts as substrate for nMOS devices.
The two areas are electrically isolated using thick field oxide (and often
isolation implants [not shown here])
Twin-Tub (Twin-Well) CMOS Process
This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently. Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics. The Twin-Tub process is shown below.
Silicon-on-Insulator (SOI) CMOS Process
Rather than using silicon as the substrate material, technologists have sought to use an insulating substrate to improve process characteristics such as speed and latch-up susceptibility. The SOI CMOS technology allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate. The main advantages of this technology are the higher integration density (because of the absence of well regions), complete avoidance of the latch-up problem, and lower parasitic capacitances compared to the conventional p & n-well or twin-tub CMOS processes. A cross-section of nMOS and pMOS devices using SOI process is shown below.