Student Seminar Report & Project Report With Presentation (PPT,PDF,DOC,ZIP)

[attachment=14656]
Company:
-- Engineer:
--
-- Create Date: 11:36:54 07/07/2011
-- Design Name:
-- Module Name: booth - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity BoothMult4 is
GENERIC(k : POSITIVE := 4);
port(multiplier, multiplicand: in std_logic_vector(k-1 downto 0);
clk: in std_logic;
ready: out std_logic;
product_result: out std_logic_vector((2*k-1) downto 0));
end BoothMult4;

architecture boothMult4Arch of BoothMult4 is
signal count: integer:=0;
begin

process(clk)
variable num: std_logic_vector(2*k downto 0):="000000000";
variable Y, Z: std_logic_vector(k-1 downto 0);
variable i:integer;
begin

if count=0 then
num := "000000000";
Y := multiplicand;
num(k downto 1) := multiplier;
end if;
if clk'event and clk='1' then

for i in 0 to (k-1) loop
if(num(1) = '1' and num(0) = '0') then
Z := num(2*k downto (k+1));
num(2*k downto (k+1)) := Z - Y;

elsif(num(1) = '0' and num(0) = '1') then
Z := num(2*k downto (k+1));
num(2*k downto (k+1)) := Z + Y;

end if;
count<=count+1;
if count=k then count<=0;
end if;
num((2*k-1) downto 0) := num(2*k downto 1);

end loop;
if count=k then
ready<='1';
product_result <= num(2*k downto 1);
else ready<='0';
end if;
end if;

end process;

end boothMult4Arch;

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(19-07-2011, 03:48 PM)smart paper boy Wrote: [ -> ]Company:
-- Engineer:
--
-- Create Date: 11:36:54 07/07/2011
-- Design Name:
-- Module Name: booth - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity BoothMult4 is
GENERIC(k : POSITIVE := 4);
port(multiplier, multiplicand: in std_logic_vector(k-1 downto 0);
clk: in std_logic;
ready: out std_logic;
product_result: out std_logic_vector((2*k-1) downto 0));
end BoothMult4;

architecture boothMult4Arch of BoothMult4 is
signal count: integer:=0;
begin

process(clk)
variable num: std_logic_vector(2*k downto 0):="000000000";
variable Y, Z: std_logic_vector(k-1 downto 0);
variable i:integer;
begin

if count=0 then
num := "000000000";
Y := multiplicand;
num(k downto 1) := multiplier;
end if;
if clk'event and clk='1' then

for i in 0 to (k-1) loop
if(num(1) = '1' and num(0) = '0') then
Z := num(2*k downto (k+1));
num(2*k downto (k+1)) := Z - Y;

elsif(num(1) = '0' and num(0) = '1') then
Z := num(2*k downto (k+1));
num(2*k downto (k+1)) := Z + Y;

end if;
count<=count+1;
if count=k then count<=0;
end if;
num((2*k-1) downto 0) := num(2*k downto 1);

end loop;
if count=k then
ready<='1';
product_result <= num(2*k downto 1);
else ready<='0';
end if;
end if;

end process;

end boothMult4Arch;

i am not getting output for this code..