06-05-2011, 03:46 PM
The C6713™ DSK builds on TI's industry-leading line of low cost, easy-to-use DSP Starter Kit (DSK) development boards. The high-performance board features the TMS320C6713 floating-point DSP. Capable of performing 1350 million floating-point operations per second (MFLOPS), the C6713 DSP makes the C6713 DSK the most powerful DSK development board.
The DSK is USB port interfaced platform that allows to efficiently develop and test applications for the C6713. The DSK consists of a C6713-based printed circuit board that will serve as a hardware reference design for TI’s customers’ products. With extensive host PC and target DSP software support, including bundled TI tools, the DSK provides ease-of-use and capabilities that are attractive to DSP engineers.
The following checklist details items that are shipped with the C6713 DSK.
TMS320C6713 DSK TMS320C6713 DSK development board
Other hardware External 5VDC power supply
IEEE 1284 compliant male-to-female cable
CD-ROM Code Composer Studio DSK tools
Technical reference manual
The C6713 DSK has a TMS320C6713 DSP onboard that allows full-speed verification of code with Code Composer Studio. The C6713 DSK provides:
A USB Interface
SDRAM and Flash ROM
An analog interface circuit for Data conversion (AIC)
An I/O port
Embedded JTAG emulation support
Connectors on the C6713 DSK provide DSP external memory interface (EMIF) and peripheral signals that enable its functionality to be expanded with custom or third party daughter boards.
The DSK provides a C6713 hardware reference design that can assist you in the development of your own C6713-based products. In addition to providing a reference for interfacing the DSP to various types of memories and peripherals, the design also addresses power, clock, JTAG, and parallel peripheral interfaces.The C6713 DSK includes a stereo codec. This analog interface circuit (AIC) has the following characteristics:
High-Performance Stereo Codec
• 90-dB SNR Multibit Sigma-Delta ADC (A-weighted at 48 kHz)
• 100-dB SNR Multibit Sigma-Delta DAC (A-weighted at 48 kHz)
• 1.42 V – 3.6 V Core Digital Supply: Compatible With TI C54x DSP Core Voltages
• 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both TI C54x DSP Buffer Voltages
• 8-kHz – 96-kHz Sampling-Frequency Support
Software Control Via TI McBSP-Compatible Multiprotocol Serial Port
• I 2 C-Compatible and SPI-Compatible Serial-Port Protocols
• Glueless Interface to TI McBSPs
Audio-Data Input/Output Via TI McBSP-Compatible Programmable Audio Interface
• I 2 S-Compatible Interface Requiring Only One McBSP for both ADC and DAC
• Standard I 2 S, MSB, or LSB Justified-Data Transfers
• 16/20/24/32-Bit Word Lengths
The TMS320C6713™ DSP compose the floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713 device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.
The 6713 DSK is a low-cost standalone development platform that enables customers to evaluate and develop applications for the TI C67XX DSP family. The DSK also serves as a hardware reference design for the TMS320C6713 DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.
Operating at 225 MHz, the C6713 delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).The DSK uses the 32-bit EMIF for the SDRAM (CE0) and daughter card expansion interface (CE2 and CE3). The Flash is attached to CE1 of the EMIF in 8-bit mode.
An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP0 is used for the codec control interface and McBSP1 is used for data. Analog audio I/O is done through four 3.5mm audio jacks that correspond to microphone input, line input, line output and headphone output. The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP1 can be re-routed to the expansion connectors in software.
A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to the CPLD registers. The registers reside at the midpoint of CE1.
The DSK includes 4 LEDs and 4 DIP switches as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers. An included 5V external power supply is used to power the board. On-board voltage regulators provide the 1.26V DSP core voltage, 3.3V digital and 3.3V analog voltages.
A voltage supervisor monitors the internally generated voltage, and will hold the boards in reset until the supplies are within operating specifications and the reset button is released. If desired, JP1 and JP2 can be used as power test points for the core and I/O power supplies.
Code Composer communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulator through the external JTAG connector.
TMS320C6713 DSP Features
Highest-Performance Floating-Point Digital Signal Processor (DSP):
Eight 32-Bit Instructions/Cycle
32/64-Bit Data Word
300-, 225-, 200-MHz (GDP), and 225-, 200-, 167-MHz (PYP) Clock Rates
3.3-, 4.4-, 5-, 6-Instruction Cycle Times
2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS /MFLOPS
Rich Peripheral Set, Optimized for Audio
Highly Optimized C/C++ Compiler
Extended Temperature Devices Available
Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core
Eight Independent Functional Units:
Two ALUs (Fixed-Point)
Four ALUs (Floating- and Fixed-Point)
Two Multipliers (Floating- and Fixed-Point)
Load-Store Architecture With 32 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Native Instructions for IEEE 754
Single- and Double-Precision
Byte-Addressable (8-, 16-, 32-Bit Data)
8-Bit Overflow Protection
Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization
L1/L2 Memory Architecture
4K-Byte L1P Program Cache (Direct-Mapped)
4K-Byte L1D Data Cache (2-Way)
256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM
Device Configuration
Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
Endianness: Little Endian/Big Endian
32-Bit External Memory Interface (EMIF)
Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM
512M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
Two Multichannel Buffered Serial Ports (McBSPs)
Two Independent Clock Zones Each (1 TX and 1 RX)
Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones
Each Clock Zone Includes:
Programmable Clock Generator
Programmable Frame Sync Generator
TDM Streams From 2-32 Time Slots
Support for Slot Bits Size8, 12, 16, 20, 24, 28, 32:
Data Formatter for Bit Manipulation
Wide Variety of I2S and Similar Bit Stream Formats
Integrated Digital Audio Interface Transmitter (DIT) Supports:
S/PDIF, IEC60958-1, AES-3, CP-430 Formats
Up to 16 transmit pins
Enhanced Channel Status/User Data
Extensive Error Checking and Recovery
Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces
Two 32-Bit General-Purpose Timers
Dedicated GPIO Module With 16 pins (External Interrupt Capable)
Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module
IEEE-1149.1 (JTAG ) Boundary-Scan-Compatible
Package Options:
208-Pin Power PAD™ Plastic (Low-Profile) Quad Flat pack (PYP)
272-BGA Packages (GDP and ZDP)
0.13-µm/6-Level Copper Metal Process
CMOS Technology
3.3-V I/Os, 1.2-V Internal (GDP & PYP)
3.3-V I/Os, 1.4-V Internal (GDP)(300 MHz only)
TMS320C6713 DSK Overview Block Diagram
The DSK is USB port interfaced platform that allows to efficiently develop and test applications for the C6713. The DSK consists of a C6713-based printed circuit board that will serve as a hardware reference design for TI’s customers’ products. With extensive host PC and target DSP software support, including bundled TI tools, the DSK provides ease-of-use and capabilities that are attractive to DSP engineers.
The following checklist details items that are shipped with the C6713 DSK.
TMS320C6713 DSK TMS320C6713 DSK development board
Other hardware External 5VDC power supply
IEEE 1284 compliant male-to-female cable
CD-ROM Code Composer Studio DSK tools
Technical reference manual
The C6713 DSK has a TMS320C6713 DSP onboard that allows full-speed verification of code with Code Composer Studio. The C6713 DSK provides:
A USB Interface
SDRAM and Flash ROM
An analog interface circuit for Data conversion (AIC)
An I/O port
Embedded JTAG emulation support
Connectors on the C6713 DSK provide DSP external memory interface (EMIF) and peripheral signals that enable its functionality to be expanded with custom or third party daughter boards.
The DSK provides a C6713 hardware reference design that can assist you in the development of your own C6713-based products. In addition to providing a reference for interfacing the DSP to various types of memories and peripherals, the design also addresses power, clock, JTAG, and parallel peripheral interfaces.The C6713 DSK includes a stereo codec. This analog interface circuit (AIC) has the following characteristics:
High-Performance Stereo Codec
• 90-dB SNR Multibit Sigma-Delta ADC (A-weighted at 48 kHz)
• 100-dB SNR Multibit Sigma-Delta DAC (A-weighted at 48 kHz)
• 1.42 V – 3.6 V Core Digital Supply: Compatible With TI C54x DSP Core Voltages
• 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both TI C54x DSP Buffer Voltages
• 8-kHz – 96-kHz Sampling-Frequency Support
Software Control Via TI McBSP-Compatible Multiprotocol Serial Port
• I 2 C-Compatible and SPI-Compatible Serial-Port Protocols
• Glueless Interface to TI McBSPs
Audio-Data Input/Output Via TI McBSP-Compatible Programmable Audio Interface
• I 2 S-Compatible Interface Requiring Only One McBSP for both ADC and DAC
• Standard I 2 S, MSB, or LSB Justified-Data Transfers
• 16/20/24/32-Bit Word Lengths
The TMS320C6713™ DSP compose the floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713 device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.
The 6713 DSK is a low-cost standalone development platform that enables customers to evaluate and develop applications for the TI C67XX DSP family. The DSK also serves as a hardware reference design for the TMS320C6713 DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.
Operating at 225 MHz, the C6713 delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).The DSK uses the 32-bit EMIF for the SDRAM (CE0) and daughter card expansion interface (CE2 and CE3). The Flash is attached to CE1 of the EMIF in 8-bit mode.
An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP0 is used for the codec control interface and McBSP1 is used for data. Analog audio I/O is done through four 3.5mm audio jacks that correspond to microphone input, line input, line output and headphone output. The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP1 can be re-routed to the expansion connectors in software.
A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to the CPLD registers. The registers reside at the midpoint of CE1.
The DSK includes 4 LEDs and 4 DIP switches as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers. An included 5V external power supply is used to power the board. On-board voltage regulators provide the 1.26V DSP core voltage, 3.3V digital and 3.3V analog voltages.
A voltage supervisor monitors the internally generated voltage, and will hold the boards in reset until the supplies are within operating specifications and the reset button is released. If desired, JP1 and JP2 can be used as power test points for the core and I/O power supplies.
Code Composer communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulator through the external JTAG connector.
TMS320C6713 DSP Features
Highest-Performance Floating-Point Digital Signal Processor (DSP):
Eight 32-Bit Instructions/Cycle
32/64-Bit Data Word
300-, 225-, 200-MHz (GDP), and 225-, 200-, 167-MHz (PYP) Clock Rates
3.3-, 4.4-, 5-, 6-Instruction Cycle Times
2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS /MFLOPS
Rich Peripheral Set, Optimized for Audio
Highly Optimized C/C++ Compiler
Extended Temperature Devices Available
Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core
Eight Independent Functional Units:
Two ALUs (Fixed-Point)
Four ALUs (Floating- and Fixed-Point)
Two Multipliers (Floating- and Fixed-Point)
Load-Store Architecture With 32 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Native Instructions for IEEE 754
Single- and Double-Precision
Byte-Addressable (8-, 16-, 32-Bit Data)
8-Bit Overflow Protection
Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization
L1/L2 Memory Architecture
4K-Byte L1P Program Cache (Direct-Mapped)
4K-Byte L1D Data Cache (2-Way)
256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM
Device Configuration
Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
Endianness: Little Endian/Big Endian
32-Bit External Memory Interface (EMIF)
Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM
512M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
Two Multichannel Buffered Serial Ports (McBSPs)
Two Independent Clock Zones Each (1 TX and 1 RX)
Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones
Each Clock Zone Includes:
Programmable Clock Generator
Programmable Frame Sync Generator
TDM Streams From 2-32 Time Slots
Support for Slot Bits Size8, 12, 16, 20, 24, 28, 32:
Data Formatter for Bit Manipulation
Wide Variety of I2S and Similar Bit Stream Formats
Integrated Digital Audio Interface Transmitter (DIT) Supports:
S/PDIF, IEC60958-1, AES-3, CP-430 Formats
Up to 16 transmit pins
Enhanced Channel Status/User Data
Extensive Error Checking and Recovery
Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces
Two 32-Bit General-Purpose Timers
Dedicated GPIO Module With 16 pins (External Interrupt Capable)
Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module
IEEE-1149.1 (JTAG ) Boundary-Scan-Compatible
Package Options:
208-Pin Power PAD™ Plastic (Low-Profile) Quad Flat pack (PYP)
272-BGA Packages (GDP and ZDP)
0.13-µm/6-Level Copper Metal Process
CMOS Technology
3.3-V I/Os, 1.2-V Internal (GDP & PYP)
3.3-V I/Os, 1.4-V Internal (GDP)(300 MHz only)
TMS320C6713 DSK Overview Block Diagram