30-04-2011, 09:21 AM
Presented by:
Arun kumar.A
Bhanuprakash.V
Kamaraj.M.K
[attachment=13068]
Bypassing-Based Multiplier Design for DSP Applications
OBJECTIVE
To design low power bypassing based multiplier for DSP applications filters then compare with row-bypassing multiplier, column-bypassing multiplier and 2-dimensional bypassing-based multiplier.
ABSTRACT
Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier,a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multiplier and the 2-dimensional bypassing multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% power dissipation with only 15% hardware overhead on the average for 4x4, 8x8 and 16x16 multipliers.
Introduction
It is well known that multipliers consume most of the power in DSP computations. Hence, it is very important for modern DSP systems to develop low-power multipliers to reduce the power dissipation. In low-power multiplier design, many research results on the switching activity reduction have been published in the literature. A simple and straightforward approach is to design a low-power FA to reduce the power dissipation of an array multiplier. The other approaches is proposed to reduce the power dissipation of functional units by interchanging dynamic operands or using partially guarded computation. On the other hand, the reduction of the power dissipation can also be achieved through the architectural modification via row bypassing or column bypassing.
Existing System
Row-bypassing multiplier
- Addition operation in a row is disabled.
Column-bypassing multiplier
- Addition operation in a row is disabled.
Low power 2-dimensional bypassing multiplier
- Addition operation in a row or column is disabled.
Disadvantages
More complicated bypass logics.
Extra correcting circuits.
Power dissipation Increases.
Area overhead is very large.
Proposed system
Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Here, To eliminate the extra correcting circuits and design the 2-dimensional bypassing process, the carry result in the previous row must be integrated in the 2-dimensional bypassing process.
STATEMENT OF WORK
Cont,.
column bypassing multiplier.
Cont,.
2 dimensional bypassing multiplier :
a low-power 2-dimensional bypassing-based multiplier, it is desired that the addition operations in the (i)-th column or the j-th row can be bypassed if the bit, ai, in the multiplicand is 0 or the bit, bj, in the multiplier is 0
Cont,.
2 dimentional bypassing multiplier.
Structure of 2 dimensional row &column bypassing multiplier
Structure of 2 dimensional using low cost bypassing multiplier
Results yet to analyze
For column-bypass multiplier
For 2-dimensional bypass multiplier
For our proposed low power 2-dimensional bypass multiplier
Arun kumar.A
Bhanuprakash.V
Kamaraj.M.K
[attachment=13068]
Bypassing-Based Multiplier Design for DSP Applications
OBJECTIVE
To design low power bypassing based multiplier for DSP applications filters then compare with row-bypassing multiplier, column-bypassing multiplier and 2-dimensional bypassing-based multiplier.
ABSTRACT
Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier,a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multiplier and the 2-dimensional bypassing multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% power dissipation with only 15% hardware overhead on the average for 4x4, 8x8 and 16x16 multipliers.
Introduction
It is well known that multipliers consume most of the power in DSP computations. Hence, it is very important for modern DSP systems to develop low-power multipliers to reduce the power dissipation. In low-power multiplier design, many research results on the switching activity reduction have been published in the literature. A simple and straightforward approach is to design a low-power FA to reduce the power dissipation of an array multiplier. The other approaches is proposed to reduce the power dissipation of functional units by interchanging dynamic operands or using partially guarded computation. On the other hand, the reduction of the power dissipation can also be achieved through the architectural modification via row bypassing or column bypassing.
Existing System
Row-bypassing multiplier
- Addition operation in a row is disabled.
Column-bypassing multiplier
- Addition operation in a row is disabled.
Low power 2-dimensional bypassing multiplier
- Addition operation in a row or column is disabled.
Disadvantages
More complicated bypass logics.
Extra correcting circuits.
Power dissipation Increases.
Area overhead is very large.
Proposed system
Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Here, To eliminate the extra correcting circuits and design the 2-dimensional bypassing process, the carry result in the previous row must be integrated in the 2-dimensional bypassing process.
STATEMENT OF WORK
Cont,.
column bypassing multiplier.
Cont,.
2 dimensional bypassing multiplier :
a low-power 2-dimensional bypassing-based multiplier, it is desired that the addition operations in the (i)-th column or the j-th row can be bypassed if the bit, ai, in the multiplicand is 0 or the bit, bj, in the multiplier is 0
Cont,.
2 dimentional bypassing multiplier.
Structure of 2 dimensional row &column bypassing multiplier
Structure of 2 dimensional using low cost bypassing multiplier
Results yet to analyze
For column-bypass multiplier
For 2-dimensional bypass multiplier
For our proposed low power 2-dimensional bypass multiplier