14-04-2011, 03:25 PM
Presented by
Aiswariya R
[attachment=12208]
JK Flip-flop
• The most versatile of the flip-flops
• Has two data inputs (J and K)
• Do not have an undefined state like SR flip-flops
– When J & K both equal 1 the output toggles on the active clock edge
Characteristics of JK flip-flop
If one input (J or K) is at logic 0, and the other is at logic 1, then the output is set or reset (by J and K respectively), just like the RS flip-flop, but on the (falling) clock edge.
If both inputs are 0, then it remains in the same state as it was before the clock pulse occurred; again like the RS flip flop.
If both inputs are high, however the flip-flop changes state whenever the (falling) edge of a clock pulse occurs; i.e., the clock pulse toggles the flip-flop.
The D FLIP FLOP
Also called:
• Delay FF
• Data FF
• D-type Latches
• ‘Delayed 1
Has only one input terminal
Can be obtained from S R by just putting an inverter between S & R terminals
The level present at D will be stored in the FF at the instant,the positive going transition occurs
Change of state occurs at positive going edge of the pulse(positive edge triggered)
Symbol
D (Delay) Flip Flop Uses
Sequential logic devices used in temporary memory devices.
Wired together to form shift registers and storage registers.
Delays data from reaching output Q one clock pulse.
CMOS examples: 74HC74, 74FCT374, 40174
Over 50 different ICs in FACT CMOS family.
Aiswariya R
[attachment=12208]
JK Flip-flop
• The most versatile of the flip-flops
• Has two data inputs (J and K)
• Do not have an undefined state like SR flip-flops
– When J & K both equal 1 the output toggles on the active clock edge
Characteristics of JK flip-flop
If one input (J or K) is at logic 0, and the other is at logic 1, then the output is set or reset (by J and K respectively), just like the RS flip-flop, but on the (falling) clock edge.
If both inputs are 0, then it remains in the same state as it was before the clock pulse occurred; again like the RS flip flop.
If both inputs are high, however the flip-flop changes state whenever the (falling) edge of a clock pulse occurs; i.e., the clock pulse toggles the flip-flop.
The D FLIP FLOP
Also called:
• Delay FF
• Data FF
• D-type Latches
• ‘Delayed 1
Has only one input terminal
Can be obtained from S R by just putting an inverter between S & R terminals
The level present at D will be stored in the FF at the instant,the positive going transition occurs
Change of state occurs at positive going edge of the pulse(positive edge triggered)
Symbol
D (Delay) Flip Flop Uses
Sequential logic devices used in temporary memory devices.
Wired together to form shift registers and storage registers.
Delays data from reaching output Q one clock pulse.
CMOS examples: 74HC74, 74FCT374, 40174
Over 50 different ICs in FACT CMOS family.